(Fwd)Wireless Technology Makes Waves In All Directions

Louis E. Frenzel | ED Online ID #17819 | January 17, 2008

Nothing is hotter now than the cell-phone business, which is driving semiconductor sales. And while cell phones are the biggest contributor to electronics growth, many other wireless technologies keep expanding as we drive toward a totally wireless society.

In 2007, annual cell-phone sales exceeded 1 billion handsets for the first time. Experts say 2008 will see 1.4 billion sales. The total number of U.S. subscribers passed 250 million in 2007, but the market is nearing saturation.

Despite this impressive number, the U.S. is small potatoes. China saw about 400 million handset sales in 2007, and that is only a fraction of the potential there. India is another growing customer, second to China in volume.

3G Rollout
Third-generation (3G) cell phones based on the ITU UMTS WCDMA standards set by the Third Generation Partnership Project (3GPP) are slowly but surely being bought and deployed, especially in the larger cities of Asia, Europe, and the U.S. The U.S. 3G rollout is going more slowly. But Qualcomm’s cdma2000 EV-DO technology, which is used by Sprint Nextel and Verizon, is helping it along.

The Rev. A and B versions of EV-DO are even faster and becoming more widely deployed in cell phones and notebook data cards. Some High Speed Packet Access (HSPA) 3G technology that boosts WCDMA connection speeds to more than 3 Mbits/s are also coming online. While 3G adoption is roughly only 50% of what it could be worldwide (even less in the U.S.), it is expected to ramp up as the carriers build out their networks and add services and as new phones become available.

Progress In 4G
The development of fourth-generation (4G) cell-phone technologies continues to progress, with the Long Term Evolution (LTE) standard apparently well in the lead for future adoption. LTE is still under development in the 3GPP, but is expected to be ratified in 2009.

This is the upgrade path that current GSM/EDGE/ WCDMA carriers like AT&T and T-Mobile will adopt in the future. It uses orthogonal frequency-division multiple access (OFDMA) and promises data speeds to 100 Mbits/s.

Qualcomm’s Ultra Mobile Broadband technology is also 4G and uses OFDMA. It is the 4G upgrade path for cdma2000 EV-DO carriers. But LTE now has the support of cdma2000 EV-DO carrier Verizon and has just about clinched the title of 4G winner.

The "Open" Movement
U.S. cell-phone carriers only offer the products and services they want you to have in their so-called “walled gardens.” Many experts say this limits their possible applications. Google wants to change this approach, intending to enter the cell-phone business and provide open products and services.

With the real possibility of Google becoming a buyer of spectrum in the forthcoming FCC auction and thus competing in the wireless business, the big carriers have beat Google to the punch. Verizon and more recently AT&T announced that they would immediately open their systems, giving subscribers a chance to buy other phones and use other applications.

Meanwhile, Google’s recent announcement of its Android Linux-based operating system software for developing open applications has generated lots of interest in developing third-party software and applications for cell phones.

The Femto Phenomenon
A recent upsurge in interest in femtocells will further roil the cell-phone business. A femtocell is a home basestation that is designed to bring superior cell coverage inside homes (see the figure). With over 50% of all cellular calls coming from inside buildings and homes, many customers have discovered just how unreliable wireless can be with multiple walls and other obstructions.

The femtocell is a full-blown basestation, but operates at low power to prevent spillover into the marco network or into your neighbor’s home. It connects to your DSL or cable TV high-speed Internet connection for backhaul to the carrier. There’s lots of interest, with carriers studying it and preparing network changes to accommodate it. While 2008 is expected to be a year of study and development, look for real femto-cell products and services in 2009.

Lost Season 4 is Coming:just 9 days!

With the return of Lost Season 4 on Thursday January 31st on ABC, I feel excited and curious about the next episode.

Feeling that their rescue is close at hand, the survivors don't know whether to believe Charlie's final message that the people claiming to liberate them are not who they seem to be. The band of friends, family, enemies and strangers must continue to work together against the cruel weather and harsh terrain if they want to stay alive. But as they have discovered during their 70-plus days on the island, danger and mystery loom behind every corner, and those they thought could be trusted may turn against them. Even heroes have secrets.......

Let's counter the days together~!

Good news and a Paradise for verification engineer:Open Verification Methodology(OVM)

How is it Open?

The OVM is available as a download by anyone, under the Apache 2.0 license. This standard, open license allows anyone to use OVM libraries for any purpose, including creation of derivative work.

Who created OVM?

The OVM is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on two-thirds of the world's SystemVerilog simulators. The OVM will also facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e (IEEE 1647) languages.

When is it available?

The OVM is available for download from this site as of January 9. 2008. Join OVM World (http://www.ovmworld.org)today to get regular updates on the OVM.

Background

Despite the availability of the IEEE 1800 SystemVerilog standard, the benefits of an open verification language have not yet been realized. The availability of multiple class libraries and methodologies have hurt the ability for true interoperability.

• Multiple class-libraries restricted interoperability
• Different language subsets
• Incompatible VIP interfaces
• Linked to just one simulator

• Multiple methodologies restricted reuse
• Prohibitive licensing limited multi-vendor support
• Incomplete and incompatible technology restricted VIP plug & play (e.g. communication, messaging and synchronization, test-writer I/F, etc.)
• Different availability of underlying SystemVerilog language constructs prevented interoperability
• Different set of language constructs implemented in each simulator
• Different evaluation of those language constructs that were aligned

Cadence and Mentor Graphics have collaborated to address these issues and to deliver an open and interoperable class library and methodology, the OVM, which delivers on the SystemVerilog promise.

Key Benefits

• Open
• Written in IEEE 1800 SystemVerilog
• Runs on any simulator supporting the IEEE 1800 standard
• Verified on Cadence’s Incisive and Mentor Graphics’ Questa Verification Platform
• True open-source license agreement (Apache 2.0)

• Interoperable
• Ensures VIP interoperability across ecosystem & simulators
• Enables VIP ‘plug and play’ functionality for designers
• Ensures interoperability with other high level languages

• Proven
• Based on Cadence’s Incisive Plan-to-Closure Methodology - URM Component and Mentor’s Advanced Verification Methodology (AVM)
• Incorporates Best Practices from >10 years of experiences

A Tcl for Tcl/Tk

Tcl/Tk - one language, many uses. It can be used for GUI(Graphical User Interface) development with the powerful TK. Tcl/Tk runs as a plugin from web browsers made by Netscape and Microsoft. So it can be used instead of JavaScript and VBScript. It is a CGI language and can be used in servers. Tcl-Tk is also extremely extendable - Tcl/Tk is valuable to C/C++ programmers who want to learn a high-level scripting language for their user interfaces or for integrating pieces of a large system.

Tcl stands for Tool Command Language. Tcl and Tk, its associated graphical user interface toolkit, was created by Professor John Ousterhout of the University of California, Berkeley. Tcl is a scripting language that runs on Windows, UNIX and Macintosh platforms. Tk is a standard add-on to Tcl that provides commands to quickly and easily create user interfaces. Even though Tcl was originally created on UNIX, your Tcl/Tk scripts should run the same on all supported platforms, except for a few differences.

Tcl is a very simple, open-source-licensed programming language and provides basic language features such as variables, procedures, and control, and it runs on almost any modern OS, such as Unix, Macintosh, and Windows 95/98/NT/XP computers.

Tcl was originally developed as a reusable command language for experimental computer aided design(CAD) tools. The interpreter was implemented as a C library that could be linked into any application. It is very easy to add new functions to the Tcl interpreter, so it is an ideal reusable "macro language" that can be integrated into many applications.

But Tcl is a programming language in its own right, which can be roughly described as a cross-breed between LISP/Scheme (with less parens) and shells (with more powerful structuring). You can write any number of programs in Tcl, just as you can in any other language. Tcl programs are usually called "scripts" because the programs do not need to be compiled into a machine-readable form.

what do I need to look for in the design, to meet Timing Qualification/Closure

what do I need to look for in the design, to meet Timing Qualification/Closure

1. Perform check design/model.
2. check how many flops are not with clocks.
3. check for any timing loop in the design
4. check whether all the Ports are constrained for input/output delays
5. Check whether all the clock-gating checks are performed.
6. Is the clock skews/clock insertions are in the limit , rather it is in the acceptable targets.
7. Did the design has setup/hold uncertainities mentioned for jitter and so on and meets timing requirements.
8. Is the Design functionaly fine in a Multi mode Design Environment
9. Is the Design meets asynchronous checks like recovery/removal.

performing a Functional Simulation with the ModelSim Software

performing a Functional Simulation with the ModelSim Software

You can run the Mentor Graphics ModelSim PE or SE software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components from the ModelSim interface or with command-line commands.


To perform a functional simulation with the ModelSim interface:

1.

If you have not already done so, set up a project with the ModelSim software.
2.
To map the design libraries to your work library:
1.

On the File menu, point to New and click Library (File menu). The Create a New Library dialog box appears.
2.

Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK.
3.

Repeat steps 2a and 2b to map altera_mf to the work library.
3.

If the Verilog HDL design contains CAM, RAM, or ROM functions, and you are using a Memory Initialization File (.mif), to convert memory initialization file for use with the ModelSim software:

1.

Export the MIF File as a RAM Initialization File (.rif) in the Quartus II software.
2.

Add parameter lpm_file = ".rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.
3.

On the Compile menu, click Compile.
4.

In the Compiler Options dialog box, click the Verilog tab.
5.

Click Macro. In the Define Macro box, type USE_RIF. In the Value box, type 1.
6.

Click OK to close the Define Macro box.
7.

Click OK.

4.

To compile the functional simulation libraries, Verilog or VHDL Design Files, and test bench files (if you are using a test bench):



Note:

*

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.
*

If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the txdigitalreset, rxanalogreset, and rxdigitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

1.
1.

On the Compile menu, click Compile.
2.

In the Library list of the Compile HDL Source Files dialog box, select the work library.
3.

In the File name list, type the directory path and file name of the functional simulation libraries.

or

In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File.
4.

Click Compile.



Note: For VHDL designs that use the 220model.vhd library, turn on Use Explicit Declarations under Default Options in the Compile dialog box. For VHDL-93 compliant designs, turn on Use 1993 Language Syntax under Default Options.

1.
5.

Repeat steps 4b to 4d to compile the Verilog or VHDL Design File.
6.

Repeat steps 4b to 4d to compile the test bench file(s).
7.

Click Done.

5.

To load the design:
1.

On the Simulate menu, click Simulate. The Simulate dialog box appears.
2.

In the Name list, click the + icon to expand the work directory.
3.

Select the top-level design file to simulate.
4.

Click Add.
5.

Click Load.
6.

Perform the functional simulation in the ModelSim software.

How to process mif file in modelsim

It's well-kown that the .mif file is the a file of Altera FPGA tools used to initiate the memory such as ROM,RAM and so on. Howerver，when you want to simulate the design in modelsim, how to process the mif file, what should you do?

Solution 1:
The ModelSim tool does not support the memory initialization file (.mif) format and requires you to generate a .hex file as specified in 1430.html. Once you have the initial memory contents specified in the .hex format, please note the following:

If you are simulating in a VHDL environment, the ModelSim tool will automatically reference the .hex file you have created and no additional steps are required.

If you are simulating in a Verilog environment, the ModelSim tool requires an additional .dll file that is included with the qu(at)rtus II software. To use this .dll file, please take the following steps:
Open the modelsim.ini file (Make sure to open the copy that the ModelSim tool is currently using. If you have a modelsim.ini in your project directory, that file will be used.)
Search for the following lines:
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl

Remove the semicolon ( from the "Veriuser" line and point to the location of the .dll file as follows:
Veriuser = \eda\mentor\modelsim\convert_hex2ver.dll
Save the changes, close the. INI file and re-start the ModelSim tool.
Note: if you are unable to save the changes, please make sure to change the permissions on the modelsim.ini file from the Properties menu.

Solution 2：

1）To turn a .mif into .hex just open the .mif in qu(at)rtus II, then save the file as a .hex and qu(at)rtus II will do the conversion.
2）modify the file.v that is generated by megaward , and then, in the file replace the .mif into the .hex.

How to solve setup and hold violation

Solving Setup violation

1. At first check whether the path is a valid path means whether this path will be exercised in your chip or it is a false path.
2. Check with the design specification whether the specified path could operate as a multicycle path rather than a single cycle path.
Assume it is a valid path.
1. Now check the wireload models used .
2. Check the loading of the high fanout nets.
3. group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
4. use various compile options try with various switches.
5. Use designware components if you have logic similar to adders/multipliers .
6. Use compile_ultra options to speed up the paths which uses different algorithms for optimizations.
7. Use the flip-flops which has lesser setup time.
8. In case if the paths or of cross clock domains check whether the path is of synchronization logic, which usually is a false path as we have synchronizers in these paths.
9. In case you could use low Vt libraries which has faster delays can be used for specific paths to close on timing.check these options whether dual Vt flow is allowed .
10. check whether these paths could be solved in timing by using useful-skew concept after place and route by optimal clocktree building.

Solving hold violation

1. By adding more delay in the data path, by adding buffers.

(FWD)EDA ESL startup Imperas close to launch

By Michael Santarini, Senior Editor -- EDN, 12/18/2007

Over the last couple of years, there’s been a lot of talk in the ESL niche of the EDA community about a small startup called Imperas Design. Since it’s founding a couple of years ago, the company has been releasing only vague details about its product direction to the press but enough information to EDA analyst Gary Smith for him to describe it as having one of the most promising product directions in years. And that’s pretty impressive, considering the company has yet to commercially release its first product. EDN has learned, however, that Imperas will introduce its product early next year, but has had to alter its focus a bit.

Certainly one of the reasons this startup has been raising expectations is because the company is being run by industry veteran Simon Davidmann, who has a track record for being with startups that have delivered significant innovations in design tools (and a knack for raising hype). Davidmann was a co-developer of the HILO language, the first RTL simulation language, which was acquired by GenRad, and was an early employee of Gateway Design Automation, the original developer of the Verilog hardware description language. Then after stints with several companies, Davidmann teamed up once again with some of the innovators from HILO and Gateway to found Co-Design, which developed Superlog, now known as SystemVerilog. Davidmann successfully sold that company to Synopsys a few years ago, and SystemVerilog has since become the de facto standard next generation HDL.

But instead of just retiring after selling Co-Design, Davidmann along with HILO and SystemVerilog co-developer Peter Flake immediately started working on a new company with high ambitions: a tool set to facilitate the programming and modeling of multi-processor core ICs.

Davidmann said the industry is littered with the bones of IC startups that created innovative multi-processor architectures but couldn’t find a way to efficiently program the chips to work effectively. In other words, software development has become the bottleneck.

One of the biggest obstacles holding back multi-core processing has been modeling. There hasn’t been a way to quickly develop processor models or a way to get models to run fast enough to allow architects and software designers to accurately create applications that take advantage of multi-processor architectures.

Thus, Imperas a few years ago set out to create a system that would do it. Initially, the company was planning on developing a tool suite to address all aspects of software development for multi-core systems. Now, however, the company has paired back plans and will first introduce a simulation and debug system and add on development tools from there.

Davidmann said the company will first focus on offering a tool for multi-processing software virtual prototype that allows users to create an executable model of chip, do performance analysis and platform optimization. This includes multiprocessing simulation, user modeling and a model library.

Davidmann is quick to note that Imperas will not be a services company. “There are several virtual prototyping companies that tend to be services companies, where they will produce the model for you,” he said. “But customers are saying ‘that’s just as bad as having a tapeout. We get the job done, then go away and after they’ve spent a lot of time talking to us, they give us model when we wanted it a year earlier.’ The current solutions out there are either a service or they are too low level.”

Davidmann said for example that SystemC is too low level and commercial tools are not appropriate for building processor models. “When you do get these environments to work, they are too slow,” said Davidmann. “You want hundreds of million instructions per second to run an application. If you got a chip running three processors at 300 MHz, that’s almost a thousand million instructions per second. A typical SystemC environment will run at 100 kilocycles to a million and that’s 1000 times slower—you just can’t develop software on that.”

Davidmann declined to give specifics of its upcoming offerings but said the company isn’t going to introduce a new language to speed up model development.

Along with the software virtual prototyping system, the company will also introduce application verification and debug environment targeted at multiprocessor core issues and quality. “Multicore processing presents all these new problems for the software guys,” said Davidmann. “Yes, you have to partition it and parallelize it, but you have a lot of communication issues you have to address. You need to have programming but now software guys also need simulation. In the hardware world we simulate everything, but more and more software guys are going to have to start simulating their applications. That also means they are going to need software debug.”

Davidmann said that originally company had planned to launch itself with two more tool offerings built on top of the MP Virtual Prototyping system and the verification and debug environment. Those offerings are a workbench, which is essentially an application programming environment to help companies manage, control, program and deliver multiprocessing application software and an ambitious tool that would provide users with a multiprocessing programming model composed of parallel application software that is correct by construction, automatically mapped and optimized to different hardware platforms.

“We think the market today is really in virtual prototyping systems, verification, and debug,” said Davidmann.

One of the big problems in the ESL space has traditionally been price points. That is, hardware design companies are used to shelling out lots of cash for tools, but software designers are used to getting tools for low or no cost. Davidmann said Imperas is and will sell its offerings to SOC companies and design groups that compose both hardware and software groups.

Davidmann said a few customers are already beta testing the tools, but the company is not planning on releasing more details of the software until it officially launches the tool sometime early next year.

Imperas was initially venture backed, but Davidmann said it recently went through a management buyout to control the company completely.

The company has 10 employees and has just brought on industry veteran EDA industry veteran Larry Lapides to head up sales.

CES 2008：the 12th and the last speech from Bill Gates

We're here! Yeah, a bit early, but this place fills some 6,000+ people. Crazy to think that this will probably be the last time Gates ever gets up on stage at CES -- at least it'll definitely be his last hurrah up there as Chairman of Microsoft.

6:25PM PT - Ok! "Ladies and gentlemen, the keynote will begin in five minutes, take your seats please."

6:28PM PT - Two minutes. "PLEASE take your seats." Let's not keep North America's 2nd richest man waiting, shall we?

6:30PM PT - Here we go! Lights are down, harp music.

6:30PM PT - Showing a CES promo video. All about the square footage, bajillions of attendees, keynote speakers -- oh, the hype.

6:33PM PT - "Ladies and gentlemen, president and CEO of the CEA, Gary Shapiro!" Mild applause. "Happy new year, and welcome to 2008 CES!"

"In my opinion, these are the best four days of the year. The floor officially opens tomorrow morning for the ribbon cutting, with cutting edge product..." Woops, teleprompter mistake in there, sorry Gary. Talking about keynotes, the CE industry forecast, and so on.

6:36PM PT - "We're hosting a new program this year..." -- Technologies in emerging countries. "And now, I'm honored to kick off 2008 CES with Microsoft's chairman, Bill Gates." Applause! Bill! "He's spoken at CES 11 times... clearly Bill's changed the world, and he's brought his vision to hundreds of millions. His story is legendary."

6:36PM PT - Xbox, Media PC, Smartphone... all products Microsoft's announced at CES. "Microsoft aims to provide the tools to let people connect no matter where they are. ... He's also the world's most successful philanthropist. ... I am proud to introduce to you... Bill Gates!" Big applause! Retro tech video playing before Bill's on.

6:38PM PT - People love playing Xbox 360, using their Media PCs, Smartphones, and Zunes alright. "Ladies and gentlemen, please welcome the Chairman of Microsoft, Bill Gates!" That's the what, third, fourth time he's been introduced?

6:39PM PT - "Good evening, it's great to be here and see all the exciting things going on... my first keynote was in 1994. That was a time when Win95 was just coming together, the internet was just getting started, and we entered the start of what we called the first digital decade. The PC installed base grew to over 1b machines..." music, photos, cellphones. "The trend here is clear: all media and entertainment will be software-driven. The first digital decade has been fantastically successful."

6:44PM PT - "We've made a lot of progress. The first digital decade has been a great success. Thousands of companies have worked together... this is just the beginning. There's nothing holding us back from going much faster and further in the second digital decade. But before we talk about that, I want to talk about the fact that this IS my last keynote.... This will be the first time since I was 17 that I won't have my full time Microsoft job.

Brian Williams: "Join us all day as we report on Bill's last full day at Microsoft." Bill drives off in a tiny car, briefcase on top. Ballmer is talking about Bill totally The Office style. Awesome. Bill spins in his chair, plays with action figures.

Matthew McConaughey: "After all these years he's finally taking work-life balance seriously. He's even got a personal trainer."

Ummm, Bill's singing "Big Pimpin'," being produced by Jay-Z. "Let me get one thing straight with you Jay-Z, you can retire, and then UNRETIRE?" Jay-Z: "Yeah, keep 'em guessing."

6:46PM PT - Bono: "Yeah, Bill, I'm a little busy here!" Bill's playing Guitar Hero II. "Bill, we've talked about this before. We're full up in the band. All positions are filled. I know... I know... I can't just replace Edge because you got a high score on Guitar Hero." "Bill's always had a passion for music... and as long as it's not my music, I'm fine with that."

Apparently now Bill's auditioning with Spielberg. "Oh Bill, what money can't buy." Clooney: "Steven, I can't play Bill Gates. Why don't you get Russell Crow to do it? Tom Hanks? Passed on that one too?"

Bill: "I was thinking the last time I was on the show it was really successful..." Jon Stewart: "Yeah, you were great. But you did kind of run off at the end, like it had monkey-pox." Clip of that classic moment, oh yes. Jon's waffling, no Jon, let Bill co-anchor!

6:48PM PT - Bill asks Hillary and Obama to be their running-mates -- Gore: "Oh hey Bill. No, it's not an INCONVENIENT time. Yeah, that was a good one."

Ozzy Osbourne: "We're the first to give credit where it's due. Microsoft Bob? All his."

Bill drives away from Microsoft one last time... all his office stuff falls off his car -- oh Bill. Another Brian Williams clip. And huuuuuge applause. Over 6k people!

6:53PM PT - "I don't think it's an accurate representation... but it was fun to put together." Gee, thanks Bill, ya don't say. "Of course, after the transition, I'll have a few projects I'll pick about the magic of software... how it will advance education and health. The second digital decade will be more focused on connecting people, more focused on being user centric. Microsoft will deliver platforms that will let people build apps -- but they'll run not only on the PC, in the cloud, on the phone, in the car, in the TV."

"We'll use the best of rich platforms and services.... these devices will span work and business. ... The three key elements I'd highlight: high def experiences everywhere. On the wall, in your desk and in your table -- it will just be there, easy to manipulate."

6:53PM PT - The quality of the rendering will be very, very rich, and will apply high quality AV... getting your data, you'll just take that for granted. No longer will users have to bridge between the devices. The master in the cloud -- backing up, searching, connecting -- will be very simple. The information can be shared in a simple way."

"When you get a new phone or want to borrow a device, it'll be a very simple thing to get up and running... organizing memories and having the system find what's relevant to you, that digital memory application will be something broadly used and very important. Devices will know your context, know your location. Finally, the third and most underestimated: the power of the natural user interface."

6:58PM PT - "We've seen new interfaces: touch on the Windows PC, touch on the iPhone." Oh? "The reaction to those natural interface implementations has been very dramatic. People are interested in a simpler way of accessing their information. All of these things come together with the other elements to create very new experiences. We're just at the beginning of this. This is something the software industry will build into the platform."

"The innovation of the previous years will come together... a key building block has been the Windows platform. We will evolve that and use it as the central building block. The last year has been an amazing year PCs. ... A year ago we launched Vista, we have 100 million people using Vista."

"We have great partners building neat, new form-factor PCs... we have online services, we're seeing incredible growth in those. Windows Mobile, over 10 million new users last year, and we'll double that next year. The phones have gotten so rich."

6:59PM PT - I want to give you a quick glimpse about the latest exciting developments." Mika Kramer (sp) has taken the stage: "My lifeline is Windows... gone are the days of multiple sign-ins and multiple hassles. With my single Windows Live ID all my services are integrated, personalized, and connected. Tonight I want to share what's fresh and new -- what helps me stay connected."

7:01PM PT - Windows Live calendar demo.

7:02PM PT - Now doing a demo of the Windows Live photo gallery...

An image of the new Palm!

7:05PM PT - Demo of Live Spaces, Live Video Search. All done!

Bill's back: "Well, I got invited to that snowboard thing, so I now I have to buy one of these things." Bill, you're such a nerd. Surface demo! Bill's talking about the recognition systems, playing with customizing the board.

Bill writes his signature on this snowboard as: "Bill!" in cursive. Nice.

Demoing Surface integration with a phone to send out to Windows Live. "We see surface showing up in many situations -- even here in Vegas -- as a new flexible interface. Another big announcement for us is the introduction of a web technology called Silverlight. It came out with some unique capabilities, shipped in its first version it got a great response."

7:08PM PT - "I'm pleased to announce today we've found a perfect partner to showcase Silverlight: NBC has chosen Microsoft has as its exclusive video partner for online video footage. We'll make it all available live and on demand." Handing off to NBC via video.

Lots of clips from the Olympics -- Bob Costas, yo Bob. NBCOlympics.com / MSN -- video on the web "in high quality and with enhanced features." Bob: "One last thing -- you HAVE to stop calling me. There's simply no place for you on our Olympic broadcast -- there's nothing I can do. Lose my number."

7:11PM PT - "I'll enjoy watching the Olympics... I can watch all the obscure sports." Robbie Bach is up! "It's good to be here again to talk about connected entertainment! I want to talk about the successes we've had in 2007 and talk about what's coming in the future... first, we'll talk about gaming."

"Vista is a great OS for gaming, and Windows is far and away the largest gaming platform -- Xbox has had tremendous success as well. 17.7m consoles shipped to date -- in the US through November we did 3.5b in business, more than the Wii and PS3.. more than the spending on Wii and PS3 combined. We also continue to grow on Xbox Live."

"We have passed the 10 million member mark -- that's six months faster than we expected to get to that number. Certainly a lot of the time people are on Live playing games, but they're also enjoying TV and movies.... ABC and Disney will be bringing their shows to Xbox Live this month. High School Musical, Lost, Desperate Housewives... We're also adding in the movie space."

7:15PM PT - MGM! "Xbox Live will provide 2x on-demand content than any cable or sat provider. Our approach to TV isn't just through Xbox -- Media Center continues its success, and is on the vast majority of PCs in the market to date." Talking about Media Center Extender tech: "New extenders from Samsung and HP -- which we already heard about last week."

Finally Mediaroom (MSFT's awesome IPTV service): "First, we have tech called DVR anywhere -- distribute recorded content around the house." Talking about interactive services with CNN. "The final announcement, last year we talked about the 360 being an STB -- this year we're excited to announce that BT will be the first to provide that capability. But a 360 and use it as an STB for your TV."

"This is not just a hobby, this is something we take quite seriously." That a dig at Jobs and the Apple TV as "Apple's hobby"? Now the Zune, comparing it to the iPod. Yep. "For the first time we'll begin selling the Zune outside the US, in Canada."

7:19PM PT - "Music is an inherently social experience, and that's why we made Zune Social." Robbie's invited a pal, Molly, up on stage to help demo Zune Social, Zune Card, etc.

Ha! Robbie's user name is EDprezz (President of Entertainment and Devices -- high-larious).

Shins, Silversun Pickups, Decemberists, it's a hipster hit parade up in this piece!

7:23PM PT - Robbie's moved on to Sync, demoing that. Robbie asks the Sync machine to play Cars by Gary Numan. Huzzah, Numan!

7:28PM PT - "The other exciting thing that's happening in the auto space is a new upgrade to Sync, which is called 911-assist. If an airbag deploys, the system automatically makes a 911 call --unless you stop it -- so emergency services can come quickly to help you out." Windows Mobile time. "Phones are going to be a BIG platform -- PCs will grow, but phones are the fastest growing platform. We outsell BlackBerry, we outsell the iPhone."

"Tellme is a leader in the telephony space, but in the future they're going to launch something called Say and See." Demoing again -- this app uses GPS and voice recognition to search local listings. Too bad this doesn't appear to be happening on a Windows Mobile phone.

Correction -- definitely not happening on a Windows Mobile phone.

Now Robbie's showing his end of the demo, receiving movie tickets from Molly's Tellme service, then previews a Cloverfield trailer. Talking how well Microsoft is in position to take advantage of integrated (mobile) advertising. Robbie wrap-up time. "Microsoft is poised to deliver. Before our big finale, I wanted to invite Bill on stage to show us the future of where we're going..."

Bill's on, showing a demo of software camera recognition -- knows Robbie owes Bill $20. Knows what it's being pointed at, can show contextual information -- like having a HUD that tells you whatever you want to know about whatever you're looking at in real space.

According to the system Steve Ballmer is, apparently, playing nickel slots. Nice. Bill's about to call up his history of CES keynotes... media, people, and information stacks of clips and data. The Rock 2001 CES keynote flashback for the launch of Xbox. Ah, nice, CES 2005 -- we were there when Conan co-hosted. "The idea is that you don't have to take a lot of manual steps -- this should just happen for you." Robbie: "Now, we have this $20 I supposedly owe you. I want to see how good you are at Guitar Hero 3." Oh snap, they're about to "jam."

Robbie's inviting Guitar Hero champion Kelley Leyone (sp). She's playing Welcome to the Jungle, and certainly a hell of a lot better than we are.

7:39 PM PT - "Well, it turns out I've got my own ringer here." He brings out the Slash. Who is actually playing Welcome to the Jungle, ha.

Robbie's already got his wallet open.

Bach: "Ladies and gentlemen, thank you very much, I'll see you again next year..." Slash is shredding, or whatever it is those guitarists do. "Cool."

Looks like that's it! So long, Bill. I've been liveblogging you since we first started Engadget, and I'm absolutely going to miss this.

Key ASIC ventures into China

KUALA LUMPUR: Integrated chip (IC) design-based Key ASIC Bhd will venture into China – Asia’s biggest consumption market for consumer electronic products – this year to provide expertise in IT and designing capabilities.

Non-executive director Lai Yit Loong said while there were good ideas provided by the Chinese design partners, they still required assistance in intellectual property (IP), building blocks of the ICs and design services.

“We are getting strong requests from them to help with the building blocks and design services. We are seeing good demand there and will continue to invest our energy in China,” he told reporters on Jan 11 after the launch of the company’s prospectus.

Key ASIC specialises on system-on-chip for consumer electronics and communications and some of the chips include those DVD, voice-over-Internet protocol (VOIP) and Wi-Fi.

Its core competency was the design optimisation capability, where the ICs can be optimised to consume lower power, deliver higher performance with a smaller die size.

It has developed IP or basic building blocks for system-on-chip, including the central processing unit and memory. Lai said Key ASIC was a local IC design house for the local fabless market, with a 39% share.

On the challenges for the consumer electronics industry worldwide and in Malaysia, he said retail spending was driven by product features and consumers would buy if the company could deliver products with good features.

He said the company targets RM31 million profit-after-tax (PAT) for its financial year ending Dec 31, 2008 (FY08) via royalties received from the subscription or recurring revenue of electronic products.

He said recurring revenue would be from sales of these products, which is expected to grow to 28% this year from 24%.

Lai said Key ASIC’s overseas business contributes almost 100% to its revenue with a significant portion originating from Taiwan and the US.

“It is critical for us to establish a stronghold there and we have started making good progress,” he said.

He said a major bulk of the company’s overseas business are channeled via its manufacturing partner SilTerra Malaysia Sdn Bhd, using Key ASIC’s IP and design services.

Gate-level Simulation and Extraction

Placement and routing involves placement of modules on chip area and routing interconnect between various modules.

Physical Verification

Due to increase in signal speed, miniaturization of features, smaller chip sizes, lower power supply voltages, there has been greater interconnect signal integrity problem. Signal delay due to interconnect delay is more significant compared to gate delay. As a result more powerful automation tools are required for layout parameter extraction, timing delay and crosstalk simulation, and power analysis.

Parasitic Extraction

Accurate extraction of on-chip parasitics is crucial due to shrinking size and increasing contribution of interconnect delay. The parasitics consist of Resistance(R), Inductance(L) and Capacitance(C). Inductance is not critical for signal propagation until transmission line effect occurs. Resistance is easy to compute using algorithms like square counting and 2D finite-difference approach. Another reason for easy resistance estimation is that one has to consider only one conductor trace at a time. On the other hand capacitance extraction requires that neighborhood conductors be considered for electromagnetic coupling effect.

Automation tools for layout parameter extraction are Cadence Dracula, Diva, and Vampire, Avanti's Star-RC, and Mentor's xCalibre and ICextract for complete resistance and capacitance extraction.

Signal Integrity

Future of high speed Integrated circuit design depends on ability to understand and predict interconnect parasitic effects and behavior. Increasing switching speed and complexity of VLSI circuits are becoming crucial factor in determining reliability and performance of an electronic system.

A high level of accuracy for interconnect behavior. estimation is complex due to

1. increase in metallization layers
2. increasing material complexity
3. higher operating frequencies.

Various aspects of signal integrity include:

1. Technology scale down : As technology takes dip into deep sub-micrometer range, lateral coupling effects between interconnects dominate compared to vertical coupling effects in micrometer technology. Aluminium has been used until recently to manufacture interconnects but increasing contribution of interconnects in signal propagation has forced IC manufacturers to replace it with material like copper with lower resistivity. As a result gain in propagation delay is almost twice. Technology scale down has introduced some new problems like complex resistance, 3-D capacitance and inductance.

2. Propagation delay: With decrease in size of technology interconnect delay increases.

3. CrossTalk:When two wire segments are closer to each other than a minimum threshold, they will interfere in each other's functioning. Signal on one wire may weaken due to electromagnetic effects of signal carried by other wire. This interference with each other's signal is called Crosstalk. With diminishing technology size Crosstalk is major contributor to high speed IC defects.

4. Crosstalk delay: is a major contributor to timing uncertainty. The simultaneous switching of the victim and the affecting signals may lead to a wide variety of phenomena. Among those most important is delay increase when the victim and aggressor signals switch in opposite directions, starting with victim signal followed by aggressor.

Static Timing Analysis mock interview Part I

This is just a mock interview : An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview.

Interviewer: Welcome

Job Seeker: thanks

(aliasing I for Interviewer and J for Job-seeker)

I : In your resume you had mentioned that are an expert in STA(Static Timing Analysis), how comfortable are you.

J: Good comfortable.

I : one basic question, what is STA.

J : STA stands for Static Timing Analysis, checks whether the Design Meeets the timing requirements, across all the timing arcs.

I : You mentioned timing Checks , what do you mean by that.

J : Setup Timing Check, Hold Timing Check, Clock-gating Check

I : Good, do you perform some checks for asynchronous stuffs or not.

J : Yes , I do perform checks , like recovery, removal.

I : what is recovery and removal check?

J : recovery is similar to setup check and removal is similar to a hold check.

I : what are the various Timing-paths you see in any chip?

J :

Path 1: Path starting from input port and ending at a Register Data

Path 2: Path starting from register output and ending at the register output

Path 3: Path starting from register output and ending at the output port

Path 4: Path starting from inputport and ending at the output port.

Path 5: Timing Source synchronous paths.

I : Good, have you come across with a report ?check_timing ?, does this was of some use to you any-time.

J : yes , as soon as i recieve database , i used to generate this report, this will guide me to know the list of flip-flops not having clocks, flip flops with multiple clocks, input port constraints missing, timing loops and things like that , It is a quiet informative report.

I : We will continue after a break, signoff for now?. continue in part 2 section. Till then To brush up the basics of Static Timing Analysis:

Songs of Lost(1th,2th,3th season)

B.B. King - Chains And Things
http://www.lost-france.com/mp3/B.B. King - Chains And Things.mp3
Tamas Bator - Voi, Che Sapete
http://www.lost-france.com/mp3/Tamas Bator - Voi, Che Sapete.mp3
Kasey Chambers - Hard way
http://www.lost-france.com/mp3/Kasey Chambers - Hard way.mp3
Otis Redding - These Arms of Mine
http://www.lost-france.com/mp3/Otis Redding - These Arms of Mine.mp3
Les McCann & Eddie Harris - Compared To What
http://www.lost-france.com/mp3/Compared to What- Les McCann & Eddie Harris.mp3
The Seeds - Pushin' Too Hard
http://www.lost-france.com/mp3/Pushin to hard-seeds.mp3
Perry Como - Catch A Falling Star
http://www.lost-france.com/mp3/Perry Como - Catch A Falling Star.mp3
Glenn Miller - Moonlight Serenade
http://www.lost-france.com/mp3/03 - Glenn Miller- Moonlight Serenade.mp3
Driveshaft - Brothers
http://www.lost-france.com/mp3/Driveshaft-Brothers.mp3
Perry Como - Papa Loves Mambo
http://www.lost-france.com/mp3/04 - Perry Como-Papa Loves Mambo.mp3
Pousette Dart Band - Fall On Me
http://www.lost-france.com/mp3/Pousette-Dart Band.mp3
The Kinks - He's Evil
http://www.lost-france.com/mp3/07 - The Kinks-he's Evil.mp3
Patsy Cline - Walkin' After Midnight
http://www.lost-france.com/mp3/Walkin' After Midnight-Patsy Cline.mp3
Skeeter Days - The End of the World
http://www.lost-france.com/mp3/05 - Skeeter Days-The End of the World.mp3
Staind - Outside
http://www.lost-france.com/mp3/06 - Staind-Outside.mp3
Dave Mathews Band - Stay
http://www.lost-france.com/mp3/Dave Mathews Band - Stay.mp3
The Drifters - Up On The Roof
http://www.lost-france.com/mp3/Up On The Roof-The Drifters.mp3
The Uniques - My Conversation
http://www.lost-france.com/mp3/My Conversation- The Uniques.mp3
Billy Joel - Easy Money
http://www.lost-france.com/mp3/01 - Billy Joel-Easy Money.mp3
The Mamas & The Papas - Make Your Own Kind Of Music
http://www.lost-france.com/mp3/mamas_papas.mp3
Patsy Cline - Leavin On Your Mind
http://www.lost-france.com/mp3/Patsy.Cline_Leavin.On.Your.Mind.mp3
Joe Purdy - Wash Away
http://www.lost-france.com/mp3/Joe.Purdy_Wash.Away.mp3
Willie Nelson - Are You Sure
http://www.lost-france.com/mp3/Willie.Nelson_Are.You.Sure.mp3
Driveshaft - You All Everybody
http://www.lost-france.com/mp3/ds.mp3
The Blind Boys of Alabama - I Shall Not Walk Alone
http://www.lost-france.com/mp3/bboa.mp3
Maggie Grace - La Mer
http://www.lost-france.com/mp3/la_mer.mp3
Damien Rice – Delicate
http://www.lost-france.com/mp3/Damien.Rice_Delicate.mp3

Verification of ASIC

Verification challeges :

Biggest challenge in IC design is verification because the cost of single error is huge. Verification is both time consuming and requires large amount of resources. Types of verification tasks can be classified into two categories :

1. functional verification : check the functionality of synthesised and optimized design against golden representation of design.
2. implementation verification : Once placement and routing is over. The design is checked for functional correctness once again. Timing and power constraints are also verified.

Black box verification methods include Simulation, and Emulation and hardware accelaration.

White box verification methods involve use of formal methods for example Assertion based Verification

Assertion Based Verification

Assertion based verification is aimed at Digital Designers. ABV is a white-box verification technique. Unlike Simulation it is not applied on the block level once the design is complete. Assertion based verification can be applied alongside design process. In-fact assertion based verification entities reside in the HDL description of the design.

Assertions are active comments embedded with in the design. Assertions turn design specification into verification objects. Assertions can be used to :

• monitor signals on interfaces that connect different blocks
• track expected behaviour of a gate, flip-flop or module
• watch for fobidden behaviour with-in a design block

Assertions are used to capture funcational specifications and assumptions of the design. An example below captures some possible assertions that can be embedded in the HDL description of the design. Since assertions travel with IP, they can be reused. Some examples of assertions are as follows :

• Invariants : To check condition like inputs A and B should never be both high.
• Sequences : If a signal A is high in one cycle then signal B should be high in next clock cycle and C must be high in next cycle.
• Eventualities : all requests have to be granted eventually. This assertion can be captured by using eventuality.

Advantages of Assertion based design :

1. Improves quality of design: assertions are "specifications" that are embedded into the design. This captures the designers intent and assumptions more closely. This also helps to define the protocol that should exist at the interface between various modules.
2. Accelerates Debugging: During its entire life cycle design can be continously checked for assertions. Assertions allows designer to check whether or not design and its environment implement interface correctly. Internal signals can be monitored to ensure that the design operates correctly.
3. IP integration is faster: IP interface with other sections of design may have problems which are easily identified by assertions. Assertions embedded in IP can identify errors in IP.

Languages Used to define assertions :

• Implicit assertions are supported by HDLs like Verilog and VHDL. These assertions are added at the time of design analysis, synthesis and HDL analysis.
• Explicit assertions are user defined assertions. Such assertions are provided by EDA vendors in form of Library like OVL. Academic languages loke CTL, LTL and automata provide a way to define explicit assertions.

Emulation and Hardware Acceleration

Emulator is a hardware device that can be used to emulate a piece of hardware functionality. It is commonly used as a debugging tool to test a system under development for functional correctness..

Emulation is a faster solution to verification problem. In Emulation a portion of emulatable design is synthesised and optimized. The compiled design is then loaded onto an emulator. Rest of the design is simulated by the workstations that are connected to the Emulator. Remember only the portion of the design that is being tested resides on the Emulator. Emulators are able to provide execution speed close to real time. This allows verification engineers to reduce verification time.

Emulation system typically consists of small number of large FPGAs. This provides multi-million ASIC-equivalent gate capacity. Such an emulation system comes as a seperate box. Emulation box can be connected to a collection of workstations using PCI card. The workstations are connected via emulation network architecture.

A complex IC is typically divided into number of different modules. Each module is develeped by a seperate team of designers. Each team verifies the functionality of its own module. The modules then go to an integration team which integrates all the modules and caries out verification. With emulation providing faster methods of design verification last minute changes can be incorporated in the design. This significantly reduces time to market.

Good news-4th Season of the Lost Starts Jan. 2008

There has been confusion around the web as to when Lost Season 4 actual starts for those wondering it is season 4 starts January 2008.

It was announced that Lost will continue for a fourth, fifth and sixth year, concluding with the 117th produced episode of the series during the 2009–2010 season. These three final seasons will consist of 16 episodes each, running weekly in the spring— uninterrupted by repeats.

Although the annoucement says that beginning with the 2007-2008 television season, the final 48 episodes of Lost will be aired as three seasons with sixteen episodes each. Thus, Lost will conclude with its sixth season. These seasons Do not start until the last Wed in January 2008 and are to air uninterrupted from February to May.

ASIC Synthesis Process

RTL Synthesis involves three major steps:

1. Transition from RTL description into gates and flip-flops
2. Optimization of logic, and
3. Placement and routing of optimized netlist.

Most of the intelligence resides in optimization stage but modern synthesis tools apply many smart techniques while converting RTL description into gates in order to reduce number of gates in the design.

Codings:

process(CLK,RST)

if(RST='1') then

Q<='0';

else if rising_edge(CLK) then

Q <= A and B and C and D;

Figure 1: RTL to gate level netlist.

Quality Metrics for ASIC Synthesis

The technology library provided by fabrication house contains basic components like sequential gates : AND, OR, NOT, NAND, NOR, XOR, BUFFER, and sequential elements like latches, flip-flops and memories. Information about cell characteristics include cell delay and area. There are three major quality metrics: area, time and power. Designer's quality metric for an IC is driven by specific application.

1. Area: With shrinking system size ASIC should be able to accommodate maximum functionality in minimum area. Designer can specify area constraint and synthesis tool will optimize for minimum area. Area can be optimized by having lesser number of cells and by replacing multiple cells with single cell that includes both functionality.

Figure 2: area optimization

2. Timing: Designer specifies maximum delay between primary input and primary output. This is taken as maximum delay across any critical path. There are three types of critical paths:

2.1 Path between a primary input and primary output.

2.2 Path from any primary input to a register.

2.3 Path from a register to a primary output.

2.4 Path from a register to another register.

3. Power: Development of hand-held devices has led to reduction of battery size and hence low power consuming systems. Low power consumption has become a big requirement for lot of designers.

Other Design rule constraints:

1. Maximum fanout for a logic element.
2. Maximum capacitance
3. slew limit - slope of signal from 20% of target to 80% of target.

RTL to FSM to Gates

First step in synthesis process is to convert a given RTL into a finite state machine. Many transformations can be applied to finite state machine in order to reduce number of states.

Figure 2: RTL to FSM(or graph)

Some of the common transformations applied to FSM are constant propagation, gate merging, dead code elimination, arithmetic merging. Next step is to generate hardware.

Figure 3: FSM(graph) to Gates.

Gate Level Logic Optimization

There are broadly two types of optimizations : Technology independent optimizations and Technology dependent optimization Technology dependent optimizations are carried out once netlist has been mapped into technology cells provided by fabrication house.

Timing and area constraints are provided by the designer. Slack is defined as difference between the expected arrival time and actual arrival time of signal at a particular output port. Slack is calculated for input to output paths. The aim of timing optimization is to reduce slack on critical paths.

Optimizations to reduce area include following :

1. Constant propagation: Boolean minimization may lead to dissolution of certain section of code into constants. Such constants should be propagated at this stage in order to reduce gate count and area.
2. Eliminate redundant logic: For example a + ab should be replaced by a.
3. 2-level SOP optimization: converting all boolean logic to 2 level sum-of-products produces very fast designs but increases area. For example (a + b) ( c + d) = ac + bc + ad + bd

Some optimizations to improve timing are as follows:

1. Restructuring: If arrival times of signals at various input gates are known, they can be re-arranged to obtain better timing delay.

Figure 4: Reauthorization to improve timing.

2. Buffer insertion to improve timing along critical path. Replacing cell with a cell of higher drive strength can improve delay along critical path.

3. Pin assignment can be changed to match the late arriving input pin with pin having faster propagation delay to output.

Figure 5: pin swapping to reduce delay.

4. False path removal. Netlist may contain false paths which are not visible in hardware description. It is important to remove these false paths in order to get accurate timing numbers and avoid wasting time in optimizing paths that are never sensitized.

Area Reclamation

Certain timing optimizations might lead to area escalation. Area Reclamation algorithms try to reclaim area which does not affect timing on critical paths.

• Downsizing the gates which contain extra pins.
• Buffers which were inserted to reach fanout constraint and are unnecessary are removed.
• Declone the cell instances which were cloned for decreasing number of fanouts.

systemverilog tutorial(Ch3 Data Types 1)

		Introduction
			SystemVerilog added lot of new data types and improved the existing data types to improve run time memory utilization of simulators. Highlights of the SystemVerilog datatypes are below
			shortint and longint data types. shortreal (real was already defined in Verilog) data type. string, chandle and class data types. logic, bit and byte data type. User defined types typedef. struct, union, and class data types. void data type. null data type. arrays, queue, associative array, dynamic array
			Next few pages we shall see the basics of this new data types, and then in later chapers we shall see the details of each of this data types.
			Integer data types
			Integer data types can be classified into 2-state types and 4-state types. 2-state types can take only 0, 1, where as 4-state types can take 0,1,X,Z. 2-state types consume less (50%) memory and simulate faster when compared to 4-state types.
			2 state value integer data types are
			shortint : 16-bit signed integer. int : 32-bit signed integer. longint : 64-bit signed integer. byte : 8-bit signed integer, can be used for storing ASCII charater. bit : User defined vector types.
			4-state value integers data types are
			logic : User defined vector types. reg : User defined vector types. wire : User defined vector types. integer : 32-bit signed integer. time : 64-bit unsigned integer.
			Integer types can be signed or unsigned, thus can change the result of a arthimetic operation. So care should be taken when declaring the data types that may be have to do arthimetic operation on it. By default byte, shortint, int, integer and longint default to signed and bit, reg, logic, and wire defaults to unsigned.
			NoteData type reg and logic are one and same. logic data type was introduced to avoid confusion with reg data type.
			Example - Integer Types
			1 module data_types(); 2 3 bit data_1bit; 4 byte data_8bit; 5 shortint data_16bit; 6 int data_32bit; 7 longint data_64bit; 8 integer data_integer; 9 10 bit unsigned data_1bit_unsigned; 11 byte unsigned data_8bit_unsigned; 12 shortint unsigned data_16bit_unsigned; 13 int unsigned data_32bit_unsigned; 14 longint unsigned data_64bit_unsigned; 15 integer unsigned data_integer_unsigned; 16 17 initial begin 18 data_1bit = {32{4'b1111}}; 19 data_8bit = {32{4'b1111}}; 20 data_16bit = {32{4'b1111}}; 21 data_32bit = {32{4'b1111}}; 22 data_64bit = {32{4'b1111}}; 23 data_integer= {32{4'b1111}}; 24 $display("data_1bit = ‰0d",data_1bit); 25 $display("data_8bit = ‰0d",data_8bit); 26 $display("data_16bit = ‰0d",data_16bit); 27 $display("data_32bit = ‰0d",data_32bit); 28 $display("data_64bit = ‰0d",data_64bit); 29 $display("data_integer = ‰0d",data_integer); 30 data_1bit = {32{4'bzx01}}; 31 data_8bit = {32{4'bzx01}}; 32 data_16bit = {32{4'bzx01}}; 33 data_32bit = {32{4'bzx01}}; 34 data_64bit = {32{4'bzx01}}; 35 data_integer= {32{4'bzx01}}; 36 $display("data_1bit = ‰b",data_1bit); 37 $display("data_8bit = ‰b",data_8bit); 38 $display("data_16bit = ‰b",data_16bit); 39 $display("data_32bit = ‰b",data_32bit); 40 $display("data_64bit = ‰b",data_64bit); 41 $display("data_integer = ‰b",data_integer); 42 data_1bit_unsigned = {32{4'b1111}}; 43 data_8bit_unsigned = {32{4'b1111}}; 44 data_16bit_unsigned = {32{4'b1111}}; 45 data_32bit_unsigned = {32{4'b1111}}; 46 data_64bit_unsigned = {32{4'b1111}}; 47 data_integer_unsigned = {32{4'b1111}}; 48 $display("data_1bit_unsigned = ‰d",data_1bit_unsigned); 49 $display("data_8bit_unsigned = ‰d",data_8bit_unsigned); 50 $display("data_16bit_unsigned = ‰d",data_16bit_unsigned); 51 $display("data_32bit_unsigned = ‰d",data_32bit_unsigned); 52 $display("data_64bit_unsigned = ‰d",data_64bit_unsigned); 53 $display("data_integer_unsigned = ‰d",data_integer_unsigned); 54 data_1bit_unsigned = {32{4'bzx01}}; 55 data_8bit_unsigned = {32{4'bzx01}}; 56 data_16bit_unsigned = {32{4'bzx01}}; 57 data_32bit_unsigned = {32{4'bzx01}}; 58 data_64bit_unsigned = {32{4'bzx01}}; 59 data_integer_unsigned = {32{4'bzx01}}; 60 $display("data_1bit_unsigned = ‰b",data_1bit_unsigned); 61 $display("data_8bit_unsigned = ‰b",data_8bit_unsigned); 62 $display("data_16bit_unsigned = ‰b",data_16bit_unsigned); 63 $display("data_32bit_unsigned = ‰b",data_32bit_unsigned); 64 $display("data_64bit_unsigned = ‰b",data_64bit_unsigned); 65 $display("data_integer_unsigned = ‰b",data_integer_unsigned); 66 #1 $finish; 67 end 68 69 endmodule You could download file data_types.sv here
			Simulation Output - Integer Types
			data_1bit = 1 data_8bit = -1 data_16bit = -1 data_32bit = -1 data_64bit = -1 data_integer = -1 data_1bit = 1 data_8bit = 00010001 data_16bit = 0001000100010001 data_32bit = 00010001000100010001000100010001 data_64bit = 0001000100010001000100010001000100010001000100010001000100010001 data_integer = zx01zx01zx01zx01zx01zx01zx01zx01 data_1bit_unsigned = 1 data_8bit_unsigned = 255 data_16bit_unsigned = 65535 data_32bit_unsigned = 4294967295 data_64bit_unsigned = 18446744073709551615 data_integer_unsigned = 4294967295 data_1bit_unsigned = 1 data_8bit_unsigned = 00010001 data_16bit_unsigned = 0001000100010001 data_32bit_unsigned = 00010001000100010001000100010001 data_64bit_unsigned = 0001000100010001000100010001000100010001000100010001000100010001 data_integer_unsigned = zx01zx01zx01zx01zx01zx01zx01zx01

VIM summary -- List of commands

List of commands

This is a list of commands that I often use. It's just a small fraction of the vim commands. But I'll add new things when I have time.

Please note that a command starting with a colon or a slash or a question mark must be ended by the Enter key -- that is not indicated in my list, while other command doesn't need the Enter key.

File and window commands

:e filename		open a new file
:e! filename		open a new file without saving the current one
:w filename		write buffer to file
:w! filename		write buffer to an existing file
:r filename		read file to buffer
:new		split window and load an empty file
:split		split window
:new filename		open file in a sub window
Ctrlww		Jump to next window
:n		Edit the next file

Moving by text objects

h		move the cursor one position left
j		move the cursor one position down
k		move the cursor one position up
l		move the cursor one position right

w		move cursor forward to first character of next word
e		move cursor forward to last character of next word
b		move cursor backward to first character of previous word
W		same as w; ignore punctuation
E		same as e; ignore punctuation
B		same as b; ignore punctuation

)		move forward to next sentence beginning
(		move backward to previous sentence beginning
}		move forward to next paragraph beginning
{		move backward to previous paragraph beginning

Move to absolute position in a line

0		move cursor to beginning of current line
$		move cursor to end of current line
^		move cursor to first non-space/tab in current line

Move to absolute position in the file

G		jump to the end of the file
gg		jump to the beginning of the file
1G		jump to the beginning of the file
nG		jump to nth line
:n		jump to nth line

Move by screen

Ctrlf		move cursor forward by one screen
Ctrlb		move cursor backward by one screen

Move to absolute position on the screen

H		move cursor to top line
M		move cursor to middle line
L		move cursor to last line

Other

''		move cursor to previous position
'x		mover cursor to marker x, where x is a letter from a to z
%		move cursor to the match of a parethesis, bracket or brace

SPACE		move cursor one position right
ENTER		move cursor to beginning of next line

Summary of inserting commands

i		change to insert mode; begin insertion at the cursor
a		change to insert mode; begin insertion after the cursor

I		change to insert mode; begin insertion at the beginning of the current line (=^i)
A		change to insert mode; begin insertion at the end of the current line (=$a)
o		change to insert mode; open a new line below the current line
O		change to insert mode; open a new line above the current line

Summary of deleting commands

x		delete one character at cursor
X		delete character in the left

D		delete from cursor to end of line
dd		delete the entire current line
dmove		delete from cursor to the location specified by the cursor motion command move. Eg: dw d2w dG dgg d0 d$ ... Try them

Summary of copying commands

Y		Copy current line to unnamed buffer
yy		Copy current line to unnamed buffer

"cyy		copy the current line to buffer named or numbered c
nyy		copy n lines below current line
"cnyy		copy n lines to buffer named or numbered c

Summary of pasting commands

p		put the contents of the unnamed buffer below the current line or after the cursor position
P		put the contents of the unnamed buffer above the current line or before the cursor position
"cp		put the contents of the buffer named or numbered c below the current line or after the cursor position c
"cP		put the contents of the buffer named or numbered c above the current line or below the cursor position c

Summary of vim replacing commands

rx		replace the character at cursor with the new character x
R		replacing by typing over (enter replace mode)
s		replace one character by insertion (enter insert mode)
C		replace from cursor to end of line (enter insert mode)
cc		replace entire current line (enter insert mode)
S		=cc
cmove		replace from cursor to move (a cursor-moving command) (enter insert mode)

Search commands

/pattern		search forward for a pattern
?pattern		search backward for a pattern
n		jump to the next occurrence of the last searched pattern
N		jump to the next occurrence of the last searched pattern in the opposite direction of the search
*		jump to the next occurrence of the word at the current cursor position
#		jump to the previous occurrence of the word at the current cursor position

Inline character search

fc		search for a character in the current line
Fc		search for a character in the current line in backward direction
;		repeat the last f or F search in the same direction
,		repeat the last f or F search in the opposite direction

Substitute command esamples

:s/old/new/		substitute the first old in current line with new
:s/old/new/g		substitute all olds in current line with new
:s/old/new/gc		substitute all olds in current line with new, with your confirm
:n1,n2s/old/new/g		substitute all olds between the two lines with new
:n1,$s/old/new/g		substitute all olds from line n1 to the end with new
:%s/old/new/g		substitute all olds with new
:%s/old/new/gc		substitute all olds with new, with your confirm

Miscellaneous commands

mc		mark current line with an letter c
'c		move cursor to the line marked with the letter c
qc...q		record a sequence of key strokes to the register c
@c		play back the key strokes recorded in register c
n@c		play back the key strokes recorded in register c n times
:rangeg/pattern/cmd		execute the cmd for each line in range matching the pattern
:rangev/pattern/cmd		execute the cmd for each line in range not matching the pattern
v		enter visual mode
V		enter visual lines mode
Ctrlv		enter visual block mode
:f		display information of the file
Ctrl-g		=:f
u		undo the most recent change
CtrlR		redo the last undone change
.		repeat the most recent command that made a change.
:!command		execute a shell command
:r!command		insert the output of a shell command after the cursor
:sh		start a shell (type exit to return to vim)

Cool commands

rENTER		break a line
J		join the current line and the next line.
~		toggle the case of the letter.
ga		show ASCII value of a character.
:as		show ASCII value of a character.
%		move cursor to match a parenthesis, bracket or brace
xp		exchanging two characters
ddp		exchanging two lines