verification coding style

1)Fork --- join
module inline_tb;
//declare variables
//instantiate designs
initial begin
initialize_design;
fork
monitor_data;
monitor_error;
monitor_timeout;
run_test;
join
end
endmodule
Note: fork-join can be implemented in the begin-end block.
2 Stimulus From Loops

initial begin
for (i = 0;i <= 255;i=i + 1）
@(negedge clk) stimulus = i;
#20 $finish;
end
3 readmemb & readmemh
TestBench作相应的定义：
Reg [7:0] A, B;
Reg Start;
……
Reg [33:0] Vector, Test_Vector[0:Test_Length];
…….
$readmemb(“Test_Fixed.v”, Test_Vector);
……
For (I=0; I 按一定时序将Test_Vector[I]送入Vector并送入A、B、Start；

Saving Power Technologies in ASIC Design

Many kinds of technologies are used in saving power in ASIC design.
Clock gating
Operand isolation
Multi-vt libraries
Multi-supply voltage
Power shutoff
Power shutoff w/ state retention
Power shutoff w/ always on buffer
Voltage/frequency scaling
RTL power estimation
Substrate biasing
Other (please specify)

Welcome to FPGAworld 2008 in Stockholm and Lund

Welcome to FPGAworld 2008 in Stockholm and Lund
You are invited to attend the 5th annual FPGAworld Conference. This years conference will take place at Electrum Kista in Stockholm Sweden on September 11 and at Ideon Lund on September 9. Please note that presentations of the academic papers will be in Stockholm on September 11.

The proceedings from FPGAworld'2007 are available in the Downloads section of www.FPGAworld.com.

We are proud to announce two very interesting keynote speakers in Lars-Erik Lundgren, Managing Director Synplicity Hardware Platforms Group, and Dr. Robert Esser, Director Xilinx Research Labs.

Following the success after last year's Innovate Nordic - Altera has launched Innovate Nordic 2008. New for this year is that Mathworks is taking part by shipping licenses for their MATLAB and Simulink tools in the packages for the registered teams. For more information please check www.innovatenordic.com. The finals will be at FPGAWorld in Kista on 11 Sept 2008.

you can see more at http://fpgaworld.com/conference/

what do I need to look for in the design, to meet Timing Qualification/Closure

what do I need to look for in the design, to meet Timing Qualification/Closure

1. Perform check design/model.
2. check how many flops are not with clocks.
3. check for any timing loop in the design
4. check whether all the Ports are constrained for input/output delays
5. Check whether all the clock-gating checks are performed.
6. Is the clock skews/clock insertions are in the limit , rather it is in the acceptable targets.
7. Did the design has setup/hold uncertainities mentioned for jitter and so on and meets timing requirements.
8. Is the Design functionaly fine in a Multi mode Design Environment
9. Is the Design meets asynchronous checks like recovery/removal.