what do I need to look for in the design, to meet Timing Qualification/Closure

what do I need to look for in the design, to meet Timing Qualification/Closure

1. Perform check design/model.
2. check how many flops are not with clocks.
3. check for any timing loop in the design
4. check whether all the Ports are constrained for input/output delays
5. Check whether all the clock-gating checks are performed.
6. Is the clock skews/clock insertions are in the limit , rather it is in the acceptable targets.
7. Did the design has setup/hold uncertainities mentioned for jitter and so on and meets timing requirements.
8. Is the Design functionaly fine in a Multi mode Design Environment
9. Is the Design meets asynchronous checks like recovery/removal.

How to solve setup and hold violation

Solving Setup violation

1. At first check whether the path is a valid path means whether this path will be exercised in your chip or it is a false path.
2. Check with the design specification whether the specified path could operate as a multicycle path rather than a single cycle path.
Assume it is a valid path.
1. Now check the wireload models used .
2. Check the loading of the high fanout nets.
3. group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
4. use various compile options try with various switches.
5. Use designware components if you have logic similar to adders/multipliers .
6. Use compile_ultra options to speed up the paths which uses different algorithms for optimizations.
7. Use the flip-flops which has lesser setup time.
8. In case if the paths or of cross clock domains check whether the path is of synchronization logic, which usually is a false path as we have synchronizers in these paths.
9. In case you could use low Vt libraries which has faster delays can be used for specific paths to close on timing.check these options whether dual Vt flow is allowed .
10. check whether these paths could be solved in timing by using useful-skew concept after place and route by optimal clocktree building.

Solving hold violation

1. By adding more delay in the data path, by adding buffers.

(FWD)EDA ESL startup Imperas close to launch

By Michael Santarini, Senior Editor -- EDN, 12/18/2007

Over the last couple of years, there’s been a lot of talk in the ESL niche of the EDA community about a small startup called Imperas Design. Since it’s founding a couple of years ago, the company has been releasing only vague details about its product direction to the press but enough information to EDA analyst Gary Smith for him to describe it as having one of the most promising product directions in years. And that’s pretty impressive, considering the company has yet to commercially release its first product. EDN has learned, however, that Imperas will introduce its product early next year, but has had to alter its focus a bit.

Certainly one of the reasons this startup has been raising expectations is because the company is being run by industry veteran Simon Davidmann, who has a track record for being with startups that have delivered significant innovations in design tools (and a knack for raising hype). Davidmann was a co-developer of the HILO language, the first RTL simulation language, which was acquired by GenRad, and was an early employee of Gateway Design Automation, the original developer of the Verilog hardware description language. Then after stints with several companies, Davidmann teamed up once again with some of the innovators from HILO and Gateway to found Co-Design, which developed Superlog, now known as SystemVerilog. Davidmann successfully sold that company to Synopsys a few years ago, and SystemVerilog has since become the de facto standard next generation HDL.

But instead of just retiring after selling Co-Design, Davidmann along with HILO and SystemVerilog co-developer Peter Flake immediately started working on a new company with high ambitions: a tool set to facilitate the programming and modeling of multi-processor core ICs.

Davidmann said the industry is littered with the bones of IC startups that created innovative multi-processor architectures but couldn’t find a way to efficiently program the chips to work effectively. In other words, software development has become the bottleneck.

One of the biggest obstacles holding back multi-core processing has been modeling. There hasn’t been a way to quickly develop processor models or a way to get models to run fast enough to allow architects and software designers to accurately create applications that take advantage of multi-processor architectures.

Thus, Imperas a few years ago set out to create a system that would do it. Initially, the company was planning on developing a tool suite to address all aspects of software development for multi-core systems. Now, however, the company has paired back plans and will first introduce a simulation and debug system and add on development tools from there.

Davidmann said the company will first focus on offering a tool for multi-processing software virtual prototype that allows users to create an executable model of chip, do performance analysis and platform optimization. This includes multiprocessing simulation, user modeling and a model library.

Davidmann is quick to note that Imperas will not be a services company. “There are several virtual prototyping companies that tend to be services companies, where they will produce the model for you,” he said. “But customers are saying ‘that’s just as bad as having a tapeout. We get the job done, then go away and after they’ve spent a lot of time talking to us, they give us model when we wanted it a year earlier.’ The current solutions out there are either a service or they are too low level.”

Davidmann said for example that SystemC is too low level and commercial tools are not appropriate for building processor models. “When you do get these environments to work, they are too slow,” said Davidmann. “You want hundreds of million instructions per second to run an application. If you got a chip running three processors at 300 MHz, that’s almost a thousand million instructions per second. A typical SystemC environment will run at 100 kilocycles to a million and that’s 1000 times slower—you just can’t develop software on that.”

Davidmann declined to give specifics of its upcoming offerings but said the company isn’t going to introduce a new language to speed up model development.

Along with the software virtual prototyping system, the company will also introduce application verification and debug environment targeted at multiprocessor core issues and quality. “Multicore processing presents all these new problems for the software guys,” said Davidmann. “Yes, you have to partition it and parallelize it, but you have a lot of communication issues you have to address. You need to have programming but now software guys also need simulation. In the hardware world we simulate everything, but more and more software guys are going to have to start simulating their applications. That also means they are going to need software debug.”

Davidmann said that originally company had planned to launch itself with two more tool offerings built on top of the MP Virtual Prototyping system and the verification and debug environment. Those offerings are a workbench, which is essentially an application programming environment to help companies manage, control, program and deliver multiprocessing application software and an ambitious tool that would provide users with a multiprocessing programming model composed of parallel application software that is correct by construction, automatically mapped and optimized to different hardware platforms.

“We think the market today is really in virtual prototyping systems, verification, and debug,” said Davidmann.

One of the big problems in the ESL space has traditionally been price points. That is, hardware design companies are used to shelling out lots of cash for tools, but software designers are used to getting tools for low or no cost. Davidmann said Imperas is and will sell its offerings to SOC companies and design groups that compose both hardware and software groups.

Davidmann said a few customers are already beta testing the tools, but the company is not planning on releasing more details of the software until it officially launches the tool sometime early next year.

Imperas was initially venture backed, but Davidmann said it recently went through a management buyout to control the company completely.

The company has 10 employees and has just brought on industry veteran EDA industry veteran Larry Lapides to head up sales.

Gate-level Simulation and Extraction

Placement and routing involves placement of modules on chip area and routing interconnect between various modules.

Physical Verification

Due to increase in signal speed, miniaturization of features, smaller chip sizes, lower power supply voltages, there has been greater interconnect signal integrity problem. Signal delay due to interconnect delay is more significant compared to gate delay. As a result more powerful automation tools are required for layout parameter extraction, timing delay and crosstalk simulation, and power analysis.

Parasitic Extraction

Accurate extraction of on-chip parasitics is crucial due to shrinking size and increasing contribution of interconnect delay. The parasitics consist of Resistance(R), Inductance(L) and Capacitance(C). Inductance is not critical for signal propagation until transmission line effect occurs. Resistance is easy to compute using algorithms like square counting and 2D finite-difference approach. Another reason for easy resistance estimation is that one has to consider only one conductor trace at a time. On the other hand capacitance extraction requires that neighborhood conductors be considered for electromagnetic coupling effect.

Automation tools for layout parameter extraction are Cadence Dracula, Diva, and Vampire, Avanti's Star-RC, and Mentor's xCalibre and ICextract for complete resistance and capacitance extraction.

Signal Integrity

Future of high speed Integrated circuit design depends on ability to understand and predict interconnect parasitic effects and behavior. Increasing switching speed and complexity of VLSI circuits are becoming crucial factor in determining reliability and performance of an electronic system.

A high level of accuracy for interconnect behavior. estimation is complex due to

1. increase in metallization layers
2. increasing material complexity
3. higher operating frequencies.

Various aspects of signal integrity include:

1. Technology scale down : As technology takes dip into deep sub-micrometer range, lateral coupling effects between interconnects dominate compared to vertical coupling effects in micrometer technology. Aluminium has been used until recently to manufacture interconnects but increasing contribution of interconnects in signal propagation has forced IC manufacturers to replace it with material like copper with lower resistivity. As a result gain in propagation delay is almost twice. Technology scale down has introduced some new problems like complex resistance, 3-D capacitance and inductance.

2. Propagation delay: With decrease in size of technology interconnect delay increases.

3. CrossTalk:When two wire segments are closer to each other than a minimum threshold, they will interfere in each other's functioning. Signal on one wire may weaken due to electromagnetic effects of signal carried by other wire. This interference with each other's signal is called Crosstalk. With diminishing technology size Crosstalk is major contributor to high speed IC defects.

4. Crosstalk delay: is a major contributor to timing uncertainty. The simultaneous switching of the victim and the affecting signals may lead to a wide variety of phenomena. Among those most important is delay increase when the victim and aggressor signals switch in opposite directions, starting with victim signal followed by aggressor.

Static Timing Analysis mock interview Part I

This is just a mock interview : An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview.

Interviewer: Welcome

Job Seeker: thanks

(aliasing I for Interviewer and J for Job-seeker)

I : In your resume you had mentioned that are an expert in STA(Static Timing Analysis), how comfortable are you.

J: Good comfortable.

I : one basic question, what is STA.

J : STA stands for Static Timing Analysis, checks whether the Design Meeets the timing requirements, across all the timing arcs.

I : You mentioned timing Checks , what do you mean by that.

J : Setup Timing Check, Hold Timing Check, Clock-gating Check

I : Good, do you perform some checks for asynchronous stuffs or not.

J : Yes , I do perform checks , like recovery, removal.

I : what is recovery and removal check?

J : recovery is similar to setup check and removal is similar to a hold check.

I : what are the various Timing-paths you see in any chip?

J :

Path 1: Path starting from input port and ending at a Register Data

Path 2: Path starting from register output and ending at the register output

Path 3: Path starting from register output and ending at the output port

Path 4: Path starting from inputport and ending at the output port.

Path 5: Timing Source synchronous paths.

I : Good, have you come across with a report ?check_timing ?, does this was of some use to you any-time.

J : yes , as soon as i recieve database , i used to generate this report, this will guide me to know the list of flip-flops not having clocks, flip flops with multiple clocks, input port constraints missing, timing loops and things like that , It is a quiet informative report.

I : We will continue after a break, signoff for now?. continue in part 2 section. Till then To brush up the basics of Static Timing Analysis:

Verification of ASIC

Verification challeges :

Biggest challenge in IC design is verification because the cost of single error is huge. Verification is both time consuming and requires large amount of resources. Types of verification tasks can be classified into two categories :

1. functional verification : check the functionality of synthesised and optimized design against golden representation of design.
2. implementation verification : Once placement and routing is over. The design is checked for functional correctness once again. Timing and power constraints are also verified.

Black box verification methods include Simulation, and Emulation and hardware accelaration.

White box verification methods involve use of formal methods for example Assertion based Verification

Assertion Based Verification

Assertion based verification is aimed at Digital Designers. ABV is a white-box verification technique. Unlike Simulation it is not applied on the block level once the design is complete. Assertion based verification can be applied alongside design process. In-fact assertion based verification entities reside in the HDL description of the design.

Assertions are active comments embedded with in the design. Assertions turn design specification into verification objects. Assertions can be used to :

• monitor signals on interfaces that connect different blocks
• track expected behaviour of a gate, flip-flop or module
• watch for fobidden behaviour with-in a design block

Assertions are used to capture funcational specifications and assumptions of the design. An example below captures some possible assertions that can be embedded in the HDL description of the design. Since assertions travel with IP, they can be reused. Some examples of assertions are as follows :

• Invariants : To check condition like inputs A and B should never be both high.
• Sequences : If a signal A is high in one cycle then signal B should be high in next clock cycle and C must be high in next cycle.
• Eventualities : all requests have to be granted eventually. This assertion can be captured by using eventuality.

Advantages of Assertion based design :

1. Improves quality of design: assertions are "specifications" that are embedded into the design. This captures the designers intent and assumptions more closely. This also helps to define the protocol that should exist at the interface between various modules.
2. Accelerates Debugging: During its entire life cycle design can be continously checked for assertions. Assertions allows designer to check whether or not design and its environment implement interface correctly. Internal signals can be monitored to ensure that the design operates correctly.
3. IP integration is faster: IP interface with other sections of design may have problems which are easily identified by assertions. Assertions embedded in IP can identify errors in IP.

Languages Used to define assertions :

• Implicit assertions are supported by HDLs like Verilog and VHDL. These assertions are added at the time of design analysis, synthesis and HDL analysis.
• Explicit assertions are user defined assertions. Such assertions are provided by EDA vendors in form of Library like OVL. Academic languages loke CTL, LTL and automata provide a way to define explicit assertions.

Emulation and Hardware Acceleration

Emulator is a hardware device that can be used to emulate a piece of hardware functionality. It is commonly used as a debugging tool to test a system under development for functional correctness..

Emulation is a faster solution to verification problem. In Emulation a portion of emulatable design is synthesised and optimized. The compiled design is then loaded onto an emulator. Rest of the design is simulated by the workstations that are connected to the Emulator. Remember only the portion of the design that is being tested resides on the Emulator. Emulators are able to provide execution speed close to real time. This allows verification engineers to reduce verification time.

Emulation system typically consists of small number of large FPGAs. This provides multi-million ASIC-equivalent gate capacity. Such an emulation system comes as a seperate box. Emulation box can be connected to a collection of workstations using PCI card. The workstations are connected via emulation network architecture.

A complex IC is typically divided into number of different modules. Each module is develeped by a seperate team of designers. Each team verifies the functionality of its own module. The modules then go to an integration team which integrates all the modules and caries out verification. With emulation providing faster methods of design verification last minute changes can be incorporated in the design. This significantly reduces time to market.

ASIC Synthesis Process

RTL Synthesis involves three major steps:

1. Transition from RTL description into gates and flip-flops
2. Optimization of logic, and
3. Placement and routing of optimized netlist.

Most of the intelligence resides in optimization stage but modern synthesis tools apply many smart techniques while converting RTL description into gates in order to reduce number of gates in the design.

Codings:

process(CLK,RST)

if(RST='1') then

Q<='0';

else if rising_edge(CLK) then

Q <= A and B and C and D;

Figure 1: RTL to gate level netlist.

Quality Metrics for ASIC Synthesis

The technology library provided by fabrication house contains basic components like sequential gates : AND, OR, NOT, NAND, NOR, XOR, BUFFER, and sequential elements like latches, flip-flops and memories. Information about cell characteristics include cell delay and area. There are three major quality metrics: area, time and power. Designer's quality metric for an IC is driven by specific application.

1. Area: With shrinking system size ASIC should be able to accommodate maximum functionality in minimum area. Designer can specify area constraint and synthesis tool will optimize for minimum area. Area can be optimized by having lesser number of cells and by replacing multiple cells with single cell that includes both functionality.

Figure 2: area optimization

2. Timing: Designer specifies maximum delay between primary input and primary output. This is taken as maximum delay across any critical path. There are three types of critical paths:

2.1 Path between a primary input and primary output.

2.2 Path from any primary input to a register.

2.3 Path from a register to a primary output.

2.4 Path from a register to another register.

3. Power: Development of hand-held devices has led to reduction of battery size and hence low power consuming systems. Low power consumption has become a big requirement for lot of designers.

Other Design rule constraints:

1. Maximum fanout for a logic element.
2. Maximum capacitance
3. slew limit - slope of signal from 20% of target to 80% of target.

RTL to FSM to Gates

First step in synthesis process is to convert a given RTL into a finite state machine. Many transformations can be applied to finite state machine in order to reduce number of states.

Figure 2: RTL to FSM(or graph)

Some of the common transformations applied to FSM are constant propagation, gate merging, dead code elimination, arithmetic merging. Next step is to generate hardware.

Figure 3: FSM(graph) to Gates.

Gate Level Logic Optimization

There are broadly two types of optimizations : Technology independent optimizations and Technology dependent optimization Technology dependent optimizations are carried out once netlist has been mapped into technology cells provided by fabrication house.

Timing and area constraints are provided by the designer. Slack is defined as difference between the expected arrival time and actual arrival time of signal at a particular output port. Slack is calculated for input to output paths. The aim of timing optimization is to reduce slack on critical paths.

Optimizations to reduce area include following :

1. Constant propagation: Boolean minimization may lead to dissolution of certain section of code into constants. Such constants should be propagated at this stage in order to reduce gate count and area.
2. Eliminate redundant logic: For example a + ab should be replaced by a.
3. 2-level SOP optimization: converting all boolean logic to 2 level sum-of-products produces very fast designs but increases area. For example (a + b) ( c + d) = ac + bc + ad + bd

Some optimizations to improve timing are as follows:

1. Restructuring: If arrival times of signals at various input gates are known, they can be re-arranged to obtain better timing delay.

Figure 4: Reauthorization to improve timing.

2. Buffer insertion to improve timing along critical path. Replacing cell with a cell of higher drive strength can improve delay along critical path.

3. Pin assignment can be changed to match the late arriving input pin with pin having faster propagation delay to output.

Figure 5: pin swapping to reduce delay.

4. False path removal. Netlist may contain false paths which are not visible in hardware description. It is important to remove these false paths in order to get accurate timing numbers and avoid wasting time in optimizing paths that are never sensitized.

Area Reclamation

Certain timing optimizations might lead to area escalation. Area Reclamation algorithms try to reclaim area which does not affect timing on critical paths.

• Downsizing the gates which contain extra pins.
• Buffers which were inserted to reach fanout constraint and are unnecessary are removed.
• Declone the cell instances which were cloned for decreasing number of fanouts.

VIM summary -- List of commands

List of commands

This is a list of commands that I often use. It's just a small fraction of the vim commands. But I'll add new things when I have time.

Please note that a command starting with a colon or a slash or a question mark must be ended by the Enter key -- that is not indicated in my list, while other command doesn't need the Enter key.

File and window commands

:e filename		open a new file
:e! filename		open a new file without saving the current one
:w filename		write buffer to file
:w! filename		write buffer to an existing file
:r filename		read file to buffer
:new		split window and load an empty file
:split		split window
:new filename		open file in a sub window
Ctrlww		Jump to next window
:n		Edit the next file

Moving by text objects

h		move the cursor one position left
j		move the cursor one position down
k		move the cursor one position up
l		move the cursor one position right

w		move cursor forward to first character of next word
e		move cursor forward to last character of next word
b		move cursor backward to first character of previous word
W		same as w; ignore punctuation
E		same as e; ignore punctuation
B		same as b; ignore punctuation

)		move forward to next sentence beginning
(		move backward to previous sentence beginning
}		move forward to next paragraph beginning
{		move backward to previous paragraph beginning

Move to absolute position in a line

0		move cursor to beginning of current line
$		move cursor to end of current line
^		move cursor to first non-space/tab in current line

Move to absolute position in the file

G		jump to the end of the file
gg		jump to the beginning of the file
1G		jump to the beginning of the file
nG		jump to nth line
:n		jump to nth line

Move by screen

Ctrlf		move cursor forward by one screen
Ctrlb		move cursor backward by one screen

Move to absolute position on the screen

H		move cursor to top line
M		move cursor to middle line
L		move cursor to last line

Other

''		move cursor to previous position
'x		mover cursor to marker x, where x is a letter from a to z
%		move cursor to the match of a parethesis, bracket or brace

SPACE		move cursor one position right
ENTER		move cursor to beginning of next line

Summary of inserting commands

i		change to insert mode; begin insertion at the cursor
a		change to insert mode; begin insertion after the cursor

I		change to insert mode; begin insertion at the beginning of the current line (=^i)
A		change to insert mode; begin insertion at the end of the current line (=$a)
o		change to insert mode; open a new line below the current line
O		change to insert mode; open a new line above the current line

Summary of deleting commands

x		delete one character at cursor
X		delete character in the left

D		delete from cursor to end of line
dd		delete the entire current line
dmove		delete from cursor to the location specified by the cursor motion command move. Eg: dw d2w dG dgg d0 d$ ... Try them

Summary of copying commands

Y		Copy current line to unnamed buffer
yy		Copy current line to unnamed buffer

"cyy		copy the current line to buffer named or numbered c
nyy		copy n lines below current line
"cnyy		copy n lines to buffer named or numbered c

Summary of pasting commands

p		put the contents of the unnamed buffer below the current line or after the cursor position
P		put the contents of the unnamed buffer above the current line or before the cursor position
"cp		put the contents of the buffer named or numbered c below the current line or after the cursor position c
"cP		put the contents of the buffer named or numbered c above the current line or below the cursor position c

Summary of vim replacing commands

rx		replace the character at cursor with the new character x
R		replacing by typing over (enter replace mode)
s		replace one character by insertion (enter insert mode)
C		replace from cursor to end of line (enter insert mode)
cc		replace entire current line (enter insert mode)
S		=cc
cmove		replace from cursor to move (a cursor-moving command) (enter insert mode)

Search commands

/pattern		search forward for a pattern
?pattern		search backward for a pattern
n		jump to the next occurrence of the last searched pattern
N		jump to the next occurrence of the last searched pattern in the opposite direction of the search
*		jump to the next occurrence of the word at the current cursor position
#		jump to the previous occurrence of the word at the current cursor position

Inline character search

fc		search for a character in the current line
Fc		search for a character in the current line in backward direction
;		repeat the last f or F search in the same direction
,		repeat the last f or F search in the opposite direction

Substitute command esamples

:s/old/new/		substitute the first old in current line with new
:s/old/new/g		substitute all olds in current line with new
:s/old/new/gc		substitute all olds in current line with new, with your confirm
:n1,n2s/old/new/g		substitute all olds between the two lines with new
:n1,$s/old/new/g		substitute all olds from line n1 to the end with new
:%s/old/new/g		substitute all olds with new
:%s/old/new/gc		substitute all olds with new, with your confirm

Miscellaneous commands

mc		mark current line with an letter c
'c		move cursor to the line marked with the letter c
qc...q		record a sequence of key strokes to the register c
@c		play back the key strokes recorded in register c
n@c		play back the key strokes recorded in register c n times
:rangeg/pattern/cmd		execute the cmd for each line in range matching the pattern
:rangev/pattern/cmd		execute the cmd for each line in range not matching the pattern
v		enter visual mode
V		enter visual lines mode
Ctrlv		enter visual block mode
:f		display information of the file
Ctrl-g		=:f
u		undo the most recent change
CtrlR		redo the last undone change
.		repeat the most recent command that made a change.
:!command		execute a shell command
:r!command		insert the output of a shell command after the cursor
:sh		start a shell (type exit to return to vim)

Cool commands

rENTER		break a line
J		join the current line and the next line.
~		toggle the case of the letter.
ga		show ASCII value of a character.
:as		show ASCII value of a character.
%		move cursor to match a parenthesis, bracket or brace
xp		exchanging two characters
ddp		exchanging two lines