New Literal Values
Introductions
SystemVerilog addes following new literal values to existing Verilog literals and improves some of the literals.
- time values
- array values
- structure values
- Improvements to string literals.
1.1 Integer and Logic Literals
Literals integer and logic values can be sized and unsized, and follow the same rules as of Verilog 2001. Assignment of constant values to any variable can be single literal as shown below.
- '0 : Set all bits to 0
- '1: Set all bits to 1
- 'X or `x : Set all bits to x
- `Z or `z : Set all bits to z
1.2 Example - Integer Literals
1 `timescale 1ns/100ps
2 module int_literals ();
3
4 integer a;
5
6 initial begin
7 $monitor ("@ ‰gns a = ‰h", $time, a);
8 a = '0;
9 #1 a = 'x;
10 #1 a = '1;
11 #1 a = 'z;
12 #1 a = 'b0;
13 #1 a = 'bx;
14 #1 a = 'b1;
15 #1 a = 'bz;
16 #1 $finish;
17 end
18
19 endmodule
Simulator Output
@ 0ns a = 00000000
@ 1ns a = xxxxxxxx
@ 2ns a = ffffffff
@ 3ns a = zzzzzzzz
@ 4ns a = 00000000
@ 5ns a = xxxxxxxx
@ 6ns a = 00000001
@ 7ns a = zzzzzzzz
2 Real Literals
The default type is real for fixed point format and exponent format. We can do type casting to covert from real values to shortreal type. Following are real literals examples.
Example - Real Literals
//------------------------------- Codes Start-------------------------------
1 `timescale 1ns/100ps
2 module real_literals ();
3
4 real a;
5 shortreal b;
6
7 initial begin
8 $monitor ("@ ‰gns a = ‰e b = ‰e ", $time, a, b);
9 a = '0;
10 b = 1.0e2;
11 #1 a = 2e5;
12 // Type casting
13 #1 b = shortreal'(a);
14 #1 a = 2.1E-2;
15 // Type casting
16 #1 b = shortreal'(a);
17 #1 $finish;
18 end
19
20 endmodule
//------------------------------- Codes END-------------------------------
Simulator Output
@ 0ns a = 0.000000e+00 b = 1.000000e+02
@ 1ns a = 2.000000e+05 b = 1.000000e+02
@ 2ns a = 2.000000e+05 b = 2.000000e+05
@ 3ns a = 2.100000e-02 b = 2.000000e+05
@ 4ns a = 2.100000e-02 b = 2.100000e-02
3 Time Literals
Time is written in integer or fixed point format, followed without a space by a time unit. The time literal is interpreted as a real time value scaled to the current time unit and rounded to the current time precision. Following are time literals examples.
Example - Time Literals
1 `timescale 100ps/10ps
2 module time_literals ();
3
4 time a;
5 initial begin
6 $monitor ("@ ‰g a = ‰t", $time, a); 7 #1 a = 1ns;
8 #1 a = 0.2ns;
9 #1 a = 300ps;
10 #1 $finish;
11 end
12
13 endmodule
Simulator Output
@ 0 a = 0
@ 1 a = 100
@ 2 a = 20
@ 3 a = 30
//（where, the time unit is 10ps）
4 String Literals
A string literal is enclosed in quotes and has its own data type. A string literal must be contained in a single line unless the new line is immediately preceded by a \. Non-printing and other special characters are preceded with a backslash. String literals can also be cast to a packed or unpacked array. SystemVerilog added following special string characters.
- \v vertical tab
- \f form feed
- \a bell
- \x02 hex number
Example - String Literals
1 `timescale 1ns/100ps
2 module string_literals ();
3
4 string a;
5
6 initial begin
7 $display ("@ ‰gns a = ‰s", $time, a); 8 a = "Hello Deepak";
9 $display ("@ ‰gns a = ‰s", $time, a); 10 #1 a = "Over writing old string";
11 $display ("@ ‰gns a = ‰s", $time, a); 12 #1 a = "This is multi line comment \
" 13 and this is second line";
" 14 $display ("@ ‰gns a = ‰s", $time, a); 15 #1 $finish;
16 end
17
18 endmodule
Simulator Output
@ 0ns a =
@ 0ns a = Hello Deepak
@ 1ns a = Over writing old string
@ 2ns a = This is multi line comment
and this is second line
5 Array literals
Array literals are syntactically similar to C initializers, but with the replicate operator ( {{}} ) allowed. The nesting of braces must follow the number of dimensions, unlike in C.
Example - Array Literals
1 `timescale 1ns/100ps
2 module real_literals ();
3
4 byte a [0:1][0:2] = {{0,1,2},{3{9}}};
5
6 initial begin
7 $display ("a [0][0] = ‰d", a[0][0]);
8 $display ("a [0][1] = ‰d", a[0][1]);
9 $display ("a [0][2] = ‰d", a[0][2]);
10 $display ("a [1][0] = ‰d", a[1][0]);
11 $display ("a [1][1] = ‰d", a[1][1]);
12 $display ("a [1][2] = ‰d", a[1][2]);
13 #1 $finish;
14 end
15
16 endmodule
Simulator Output
a [0][0] = 0
a [0][1] = 1
a [0][2] = 2
a [1][0] = 9
a [1][1] = 9
a [1][2] = 9
6 Structure Literals
Structure literals are syntactically similar to C initializers. Structure literals must have a type, either from context or a cast. When an array of structures is initialized, the nested braces should reflect the array and the structure.
Example - Struct Literals
1 `timescale 1ns/100ps
2 // Type define a struct
3 typedef struct {
4 byte a;
5 reg b;
6 shortint unsigned c;
7 } myStruct;
8
9 module struct_literals ();
10
11 myStruct object = {10,0,100};
12
13 myStruct objectArray [0:1] = {{10,0,100},{11,1,101}};
14
15 initial begin
16 $display ("a = ‰b b = ‰b c = ‰h", object.a, object.b, object.c);
17 object.a = 15;
18 $display ("a = ‰b b = ‰b c = ‰h", object.a, object.b, object.c);
19 object.c = 16'hDEAD;
20 $display ("a = ‰b b = ‰b c = ‰h", object.a, object.b, object.c);
21 $display ("Printing array of objects");
22 $display ("a = ‰b b = ‰b c = ‰h",
23 objectArray[0].a, objectArray[0].b, objectArray[0].c);
24 $display ("a = ‰b b = ‰b c = ‰h",
25 objectArray[1].a, objectArray[1].b, objectArray[1].c);
26 #1 $finish;
27 end
28
29 endmodule
Simulator Output
a = 00001010 b = 0 c = 0064
a = 00001111 b = 0 c = 0064
a = 00001111 b = 0 c = dead
Printing array of objects
a = 00001010 b = 0 c = 0064
a = 00001011 b = 1 c = 0065
Labels: Systemverilog_Tutorial
