Duplicating Registers Method

A technique commonly used to increase the speed of a critical path is to duplicate a register to reduce the fan-out of the critical path. Because FPGAs are register-rich, this is usually an advantageous structure since it can often be done at no extra expense to the design.

Example 2
– Verilog Example of Register with 64 Loads
module high_fanout(in, en, clk, out);
input[63:0]in;
inputen, clk;
output[63:0] out;
reg[63:0] out;
regtri_en;
always @(posedge clk) tri_en = en;
always @(tri_en or in) begin
if (tri_en) out = in;
else out = 64'bZ;
end
endmodule



Example 3 – Verilog Example of After Register Duplication to Reduce Fan-out
module low_fanout(in, en, clk, out);
input[63:0] in;
input en, clk;
output[63:0] out;
reg[63:0] out;
regtri_en1, tri_en2;
always @(posedge clk) begin
tri_en1 = en; tri_en2 = en;
end
always @(tri_en1 or in)begin
if (tri_en1) out[63:32] = in[63:32];
else out[63:32] = 32'bZ;
end
always @(tri_en2 or in) begin
if (tri_en2) out[31:0] = in[31:0];
else out[31:0] = 32'bZ;
end
endmodule