Static Timing Analysis mock interview Part I

This is just a mock interview : An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview.

Interviewer: Welcome

Job Seeker: thanks

(aliasing I for Interviewer and J for Job-seeker)

I : In your resume you had mentioned that are an expert in STA(Static Timing Analysis), how comfortable are you.

J: Good comfortable.

I : one basic question, what is STA.

J : STA stands for Static Timing Analysis, checks whether the Design Meeets the timing requirements, across all the timing arcs.

I : You mentioned timing Checks , what do you mean by that.

J : Setup Timing Check, Hold Timing Check, Clock-gating Check

I : Good, do you perform some checks for asynchronous stuffs or not.

J : Yes , I do perform checks , like recovery, removal.

I : what is recovery and removal check?

J : recovery is similar to setup check and removal is similar to a hold check.

I : what are the various Timing-paths you see in any chip?

J :

Path 1: Path starting from input port and ending at a Register Data

Path 2: Path starting from register output and ending at the register output

Path 3: Path starting from register output and ending at the output port

Path 4: Path starting from inputport and ending at the output port.

Path 5: Timing Source synchronous paths.

I : Good, have you come across with a report ?check_timing ?, does this was of some use to you any-time.

J : yes , as soon as i recieve database , i used to generate this report, this will guide me to know the list of flip-flops not having clocks, flip flops with multiple clocks, input port constraints missing, timing loops and things like that , It is a quiet informative report.

I : We will continue after a break, signoff for now?. continue in part 2 section. Till then To brush up the basics of Static Timing Analysis: