Parameter usage(Verilog-2001 VS Verilog-1995)

Let's set an example to indicate these differeces bewtween Verilog-1995 and Verilog-2001.

Example1 :

module myreg (q, d, clk, rst_n);
parameter Trst = 1,
Tckq = 1,
SIZE = 4,
VERSION = "1.1";
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= #Trst 0;
else q <= #Tckq d;
endmodule


module bad_wrapper (q, d, clk, rst_n);
output [7:0] q;
input [7:0] d;
input clk, rst_n;
// illegal parameter passing example
myreg #(.,.,8) r1 (.q(q), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

In order to use the parameter redefinition syntax when instantiating a module, all parameter values up to and including all values that are changed, must be listed in the myreg instantiation. For the module of Example 1, the first two parameter values must be listed, even though they do not change, followed by the new value for the
SIZE parameter, as shown in Example 2.

module good_wrapper (q, d, clk, rst_n);
output [7:0] q;
input [7:0] d;
input clk, rst_n;
// the first two parameters must be
// explicitly passed even though the
// values did not change
myreg #(1,1,8) r1 (.q(q), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

Aware of this limitation, engineers have frequently rearranged the order of the parameters to make sure that the most frequently used parameters are placed first in a module, similar to the technique described by Thomas and Moorby[4].

Despite the limitations of Verilog-1995 parameter redefinition, it is still the best supported and cleanest method for modifying the parameters of an instantiated
module. Verilog-2001 actually enhances the above parameter redefinition capability by adding the ability to pass the parameters by name, similar to passing port connections by name.

Example 2: to indicate how to instant myreg in Verilog-2001

module demuxreg (q, d, ce, clk, rst_n);
output [15:0] q;
input [ 7:0] d;
input ce, clk, rst_n;
wire [15:0] q;
wire [ 7:0] n1;
not u0 (ce_n, ce);
regblk #(.SIZE( 8)) u1
(.q(n1), .d (d), .ce(ce),
.clk(clk), .rst_n(rst_n));
regblk #(.SIZE(16)) u2
(.q (q), .d({d,n1}), .ce(ce_n)
.clk(clk), .rst_n(rst_n));
endmodule
module regblk (q, d, ce, clk, rst_n);
parameter SIZE = 4;
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input ce, clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else if (ce) q <= d;
endmodule