Systemverilog Tutorial(Ch1-intorduction)

Today is the first day of 2008!

Happy New Year For Everyone!

Now Let us make a closed study on the systemverilog.

Several days ago, I came acrossed a book called "Systemverilog Assertion". The preface of the book intrigues my interest on Systemverilog that may be the next generation hardware description language. It is reported that the systemverilog has fixed its roots steadily in EDA field such as system design and verifications of ASIC/IC design.

So it is necessary for us to make a acquaintance with it. Now I have googled many resources about it and sort them as follows step by step! Just follow me! Be patient and systemverilog world is coming.

The following chapter is about the introductions of systemverilog.

		Introduction
		Verilog 1995 version has been in market for a very long time. IEEE extended the features of Verilog 1995 and released it as Verilog 2001. But this was no good for verification engineers, so verifcation engineers had to use languages like "e", VERA, Testbuider. It was rather painfull to have two language, one for design and other for verification. SystemVerilog combines the Verification capabilties of HVL (Hardware Verification Language) with ease of Verilog to provide a single platform for both design and verification.
		Some of the new features in SystemVerilog are as listed below.
		C type data types like int, typedef, struct, union, enum. Dynamic data types : struct, classes, dynamic queues, dynamic arrays. New operators and built in methods. Enhanced flow control like, foreach, return, break, continue. Semaphores, mailboxes, event extensions. classes for object oriented programming. Assertions. Coverage. VPI extensions.
		Now IEEE has accepted the SystemVerilog, and it is called 1800-2005 standard.
		Anyone with background of C++, or OO programming language will feel at home with SystemVerilog. But on other hand if you have been thinking C or C++ is not required, then you may be shocked to know that SystemVerilog is very much like C++.

DC & PhyC .synopsys_dc.setup file

set search_path [list . /usr/golden/library/std_cells]
settarget_library [list ex25_worst.db]
setlink_library "*, ex25_worst.db ex25_best.db"
setsymbol_library [list ex25.sdb]
setphysical_library[list ex25_worst.pdb]

define_name_rules BORG–allowed {A-Za-z0-9_} –first_restricted “_” –last_restricted “_” -max_length 30 –map {{“*cell*”, “mycell”}, {“*–return”, “myreturn”}}

set bus_naming_style %s[%d]
set verilogout_no_tri true
set verilogout_show_unconnected_pins true
set test_default_scan_style multiplexed_flip_flop

Fwd:Query Yourself before Architecting a Chip

This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

• What is the targetted market for this Chip.
• What are the competitor's to this Chip and Market Requirement and ROI
• What is the Fabrication Unit the Chip is targetted for?
• What is the Success rate and Yield numbers achieved in the Fabrication Unit
• What is the technology Process targetted for
• What is the correlation of the library models w.r.t. Silicon
• What are the various Protocols the Chip is going to address
• Hardware & Software Parti-tioning.
• What is the processor/micro-controller suitable for this application.
• What is the bus-architecture targetted
• What is the performance targets for this bus architecture
• What are the various Interfaces the Chip is having
• Is the design going to be in single Vt or with Multi-Vt design
• Is using Embedded macro's right choice or Memory Macros
• What are the IP's are going to be Re-usued
• What are the IP's going to Hard-macro's
• What is the Verification Status and corner-case coverage of the I.P's
• What is the Die-size targetted/Estimated for the Chip
• What is the Power targets
• Is Power Management Unit a requirement in the chip to reduce Dynamic power
• What are the mechanisms followed to reduce the leakage power
• Is Module enables/clock-gating a part of the Methodology
• Is resets going to synchronous or asynchronous
• What are the various Synchronous Mechanisms for data-transfer's
• How many clock-domains required for the Chip
• How many PLL's are required or single PLL sufficient for all the clocks required
• What is the thought process behind PAD's Is LVTTL/SSTL pads
• Is the package going to wire-bond or Flip-chip
• Methodology for Optimal Power-grid design
• What are the noise reducing Mechanism's in case of analog integration
• Is there any requirement of speed monitor's or process checking blocks
• What is the type of fuses used laser fuse or efuses
• Is there any requirement of Fib Cells in the Design
• What are the mechanism's used to handle ESD
• what is the reliability target of the Chip and how it is addressed
• What are the Mechanisms used for Yield improvement
• Is the chip tested at at-speed test
• How much Memory-map is allocated for the IP's
• What is the metric for spare-gates in the Chip for ECO's
• Is repairable memories required
• What is the tester targetted and the requirement to the Chip in terms of Scan-chain
• Is test-vector compression mechanism's a requirement
• What is the PLL performance in terms of Jitter
• What is the Interrupt handling mechanism with in the Chip.
• What is the ROM-Code for the Chip.
• What is the Chip utilization targets
• Will the chip be routable or any requirement for special libraries with different routing tracks.
• What is the Methodology for tools and versions
• What is the Version control mechanism planned for data handling across multi Geographical Environments.
• What is the signoff criteria for the Chip
• What is the frequency targets for the Chip.
• Is there room for further revisions of the Chip.
• If the Chip has DDR/SDR interface is there any requirement for DLL.
• What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.
• What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

VIM Study(3)--Modify text

Insert text

To insert the characters you typed into the file, you need to change from command mode to insert mode. The two basic ways are i command and a command. which begin insertion right at the cursor or after the cursor. But there are several other commands (I A o O) which are very useful.

Insert right here -- i

i means "insert". It switches your mode to insert mode and begin insertion at the current position of the cursor.

Insert after the cursor -- a

a means "append". It moves the cursor forward by one character and switches your mode to insert mode. Therefore insertion begins after the position of the cursor when you pressed the a command.

Usually this is equivalent to li, move cursor to right and enter insert mode. However, to insert at the end of the line you must use command a or A, since you cannot move cursor beyond the last character of the current line.

Insert at the beginning of the current line -- I

This is equivalent to ^i

Insert at the end of the current line -- A

This is equivalent to $a

Insert a new line below the current line -- o

If you haven't learned this command, perhaps you often move the cursor to the end of the line, enter insert mode and press Enter. Well, that's what o command does -- AEnter

Insert a new line above the current line -- O

Delete text

To do deleting, keep yourself in command mode.

Delete the character at the cursor position -- x

This is the most often used deletion command. To delete a character, use cursor motion commands to move the cursor to that character and press x.

Delete the character at the left of the cursor -- X

I don't use this one since I think typing hx is easier than making an upper case X.

Delete all the stuff from cursor to end of line -- D

This one can be very handy. But if you want to change the stuff from the cursor position to the end of line, using C might be even better, which is equivalent to DA.

Delete the whole current line -- dd

You must learn this command. It makes you feel power. If you have several lines of text to delete, you can keep hitting dd and watch the lines disappearing. If you overdid it and removed some useful stuff, don't panic -- keep pressing u the removed lines will reappear in reverse order. u means "undo". vim has multiple levels of undo.

Combine a move and the delete command -- dmove

Pressing d followed by a cursor motion command will delete all the text from the current cursor position to the position the move command pointed. This will make lots of magical commands

dw		delete from cursor to end of the word
dW		delete 1 word, including punctuation characters, if any.
d10w		delete 10 words (=10dw
d0		delete from cursor to start of line
d$		=D
dG		delete from current line to end of editing buffer
d1G		delete from current line to beginning of editing buffer

Replace or change text

Replacing means removing some text and beginning inserting new text. This is equivalent to deleting first and then entering insert mode. But the saving of a couple of keystrokes can make you feel really good.

Change a single character -- r

This is a magic command that you must know. To change the character at the cursor position, just press r followed by the new character you want. The magic part is that you're still in command mode.

Replace all stuff from cursor to the end of the line -- C

Get rid of all stuff from cursor to the end of line, and begin inserting new text.

Replace by typing over -- R

Enter the replace mode. The character you're typing replaces the one at cursor position, and the cursor moves forward.

Replace a word -- cw

Remove the word at the cursor, and beginning inserting new one.

A story from a golden songbird

Once upon a time there was a golden songbird that lived in a beautiful garden. It spent all its days singing the loveliest songs to the honor of its maker and the delight of all the people who heard it.

But the keeper of the garden, who was a foolish and greedy man, coveted the little songster, and one day he made a cunning net in which he snared it. The little bird begged the man to release him and promised to tell him three great secrets if only he would let him go. Now the gardener really was a very greedy man and rubbing his hands together, he eagerly released the bird.

Then the songbird told him it’s three great secrets:
Never believe all that you hear.
Never regret what you have never lost.
Never throw away that which you have in your keeping.

The gardener was furious when he heard this and said he had known these so-called ‘secrets’ since he was a little child and shouted that the bird had tricked him. But the songbird quietly replied that if the man had really known these three secrets, or only the last of them, he would never have let him go.

Then the bird added:
“I have a most precious jewel weighing over three ounces hidden inside me and whoever possesses that marvellous stone will have every wish granted.”

On hearing this, the keeper roared like a lion and cursed himself for setting the songster free. But the little bird only added fuel to his rage by explaining that since he weighed no more than half an ounce at most, as anyone with eyes could plainly see, how was it possible that a gem weighing more than three ounces could be hidden within it’s tiny body?

At that the man tore his hair and lunged at the bird in a towering rage, but the little songbird flew to a nearby branch and added sweetly:
“Since you never had the jewel in your hands you are already regretting what you never lost, and believing what I told you, you threw it away by setting me free.”
Then the little songbird told the man to study well these three great secrets and so become as wise as the bird himself!

a philosophical story

Yesterday evening, my roommate Wang told me a philosophical story. So I write it down to share with you, may you enjoy it.

once upon a time, a billionaire made a bet on money with a poor intellectual. The billionaire would give the one billion dollars if the intellectual could do nothing except for reading books, eating and sleeping in ten years. The intellectual gave his words to the billionaire. And then, the poor intellectual was locked in a small house full of a great variety of books including literatures, philosophies, physics, medics and so forth. The sole occupation of the intellectual is reading the books day after day, however, he didn't take that as a tedium thing but find a lot of things which fascinated him very much.

With time flies, it was only a month before the deadline of the ten years. However, on account of failures of investment and business, the billionaire was bankrupt. He had no money to pay the intellectual. So the billionaire had a guy to murder the poor intellectual. When the murder got to the house which the intellectual lived during the these ten years, he found that the intellectual had escaped via breaking through the window, and left a letter on the desk. As a matter of fact, the intellectual had heard the billionaire's bankruptcy and predicted that the billionaire would had him died, so he escaped without reclaiming his money. The letter reads:
”Dear Sir,
Hi, a long time on see. I am so sorry to hear your bankruptcy. It is unnecessary for you to kill me, because I have decided to give up the money of the bet. Because I don't need your money any more, at present, I can earn lots of money by myself through the knowledges I have acquired by reading these years. Thank you for your bet and books. To a certain extent, you have paid me and the money will not run out forever. ”

A Good Verilog Coding Style

A Good Verilog Coding Style is a prime requirement in every Design, for predictable results, and reusing the codes for various applications.

• Indent the code so that the code is readable.
• Ensure the code is generic across all technologies and not specified to a single technology.
• Ensure the consistent signal names across the hierarchy.
• Ensure that each RTL file contains file headers as comment comprising of { Name of the RTL, Version tag, Authors involved and their email-id's , information about the paramets used in the constructs, last edited, Bug-fixes history, Brief about what the code is performing}.
• Ensure only one verilog statement per line.
• Ensure that speed-critical logics are in seperate module.
• Maximize the usage of gated-clocks, as this saves power.
• Prefer clock-generating circuitry in separate module files.
• Ensure one port declaration on one line, followed by comments about the port.
• Preserve port order.
• Declare the internal nets in the design.
• Limitation on the line length {for example:not more than 75}.
• Avoid the usage of 'include construct.
• Ensure that the power-downed signals are in a known state.
• Ensure that the coding style does not contain combinational feedback loops.
• Never assign "x" value to the signals.
• Maximize the usage of parameters instead of text-macros.
• Use parameters for state-encoders.
• Ensure that the design coding does not generate tri-state logic.
• Use the concept of base+offset for coding address busses.
• Tie the un-used bits to a known value.
• Connect based on port-names while instantiating.
• Ensure that no access of nets and variables outside the module context.
• Avoid using ports of type "inout" in the design.
• Ensure that the latches are transparent during scan-phase.
• Ensure that the PLL bypass is present to verify with out PLL's.
• Minimize top-level glue logic coding style.
• Ensure only one module is defined in a file.
• Ensure that the active low signals are suffixed with '_b' and clocks named with domain names for example clock_a, clock_b, "_z" for high impedance signals, "_o" for output signals, "_i" for input signals, "_ns" for state-machine next states, "_se" for scan-enable signals.
• Prefer using case statements, instead of using long if and else statements.
• Ensure that default statement is used in the case statements.
• While designing FSM behaviours , prefer three always blocks(1. register definitions. 2. Defining next-logic. 3. Defining outputs).
• Ensure that the unused module inputs are driven and not floating.
• Ensure that the design has enough amount of spare-logic to incorporate the last minute design bug-fixes.
• Ensure that the same test-benches are used for RTL and gate level simulations.
• Ensure that the design does not contain initial blocks and delay elements.
• Ensure that the whole design is resetable to a known state. No internal logic generated asynchronous resets.
• Ensure the reset is not a late arriving signal w.r.t clocks due to dense reset trees.
• In case if the desired reset is an asynchronous signal, ensure that it is part of the sensitivity list as according to the verilog if the reset signal is not part of the sensitivity list then it is inferred as a synchronous reset.
• As in the case of an synchronous reset design, assist the synopsys synthesis tool with the comment //synopsys sync_set_reset_n "rst_n" , As for the synthesis tool reset is also treated as any other signal in case of synchronous-resets. In case of synchronous reset designs, in order to maintain the pulse-width of the signal, a small counter type of circuit is required.
• Extra care is required while designing with synchronous resets and also designs having clock-gating logic. Poor coding styles can make the design non-resetable as it may be blocking the clocks reaching .
• Ensure that a situation doesn't trigger an asynchronous set and asynchronous resets for the same flip-flop.
• Ensure that the de-assertion of the asynchronous resets is not close to the clock-edge so that the flip-flop could be prevented from being entering in to meta-stable state.
• Ensure that a recovery and removal timing checks are performed for resets to ensure the optimal behaviour.
• Even though the design is working with asynchronous reset style, Ensure that the resets are synchronized passing through synchronizers. Ensure that these synchronizer flops are not part of the scan-chain stitching in the design.
• Ensure that the resets are not used as data or clock signals in the design.
• Ensure that the reset is priority over any other signal in the case of an if-else construct.
• Ensure that the signals which cross the clock-domains are synchronized.
• Ensure that the design does not contain while statements.
• Understanding the signals & functionalities based on the signal names (like For Clock definitions naming the signal with "clk", naming resets with "res", and to know the whether the signal is active-high or active low triggerred( For example : resets which are active-low are named with res_n).
• Ensure that clock-dividers are by-passed during scan stitching.
• Coding style which is generic and re-usuable.
• Avoid using verilog UDP in the design.
• Coding style which will not have simulation and synthesis mis-match results.
• Coding style friendly to Synthesis and not having constructs which synthesis tool cannot understand.
• Coding style which ensures the correct digital logic will be generated after performing synthesis. The basic digital mismatches could be inferred (For example : Latch for a Flip-flop requirement, Priority Encoder for a Mux Design requirement).
• Coding Style which are DFT(Design for Test) friendly.

Usage of Blocking(=) & Non-blocking(<=) statements and Steps to prevent Race-conditions .

Race conditions are situations, where the order of execution isn't always guaranteed within verilog.

• Use blocking statements for coding combinational logic
• Use non-blocking statements for coding sequential logic
• Never mix blocking and non-blocking in a same procedural block
• Never assign a value to the same variable multiple times in different always blocks. Even though it is a non-blocking statements the design is prone to race-condition
• To get to know more depth in to the concept Refer the paper:

Be Sensitive about the Sensitivity list

• Synthesis tools assumes to generate combinational logic from an always block, if it does not contain statements like "posedge" or "negedge".
• Ensure that a complete list of signals present in the sensitivity list in an always block, thereby the simulation results for a pre-synthesis versus the post-synthesis match.
• Ensure only one clock per sensitivity list.

Synopsys Full-case and parallel case directives

Synopsys full_case directive :

When the Synthesis tool(Synopsys Design Compiler), comes across with the comment

(//synopsys full_case, before case statements), the tool is guided stating that though all the cases are not mentioned , these are the possible cases design can honour so the tool for the rest of the non-listed cases the synthesis tool assumes that the outputs are don't cares.

(synopsys parallel_case, before case statements), the tool is guided stating that it optimizes the logic, assuming that the case statements would match only one case , prevents the synthesize tool from optimizing the un-necessary logic.

Various ways of Coding the same logic (for example :Mux)

// first example with continuous assignment

wire z;

assign z = sel ? x : y;

// second example with if and else

reg output;

always @ (x or y or sel)

if (sel)

output = x;

else

output = y;

Unsupported Verilog Language Constructs

Synthesis tool does not support the following Verilog Constructs:

Unsupported definitions and declarations

• Primitive definition
• time declaration
• Ranges and arrays for integer declarations.
• event declarations
• triand, trior, tri1, tri0 and trireg net type
• Ranges and arrays for integers.

Statements not supported by synthesis tool

• defparam statement
• initial statement
• repeat statement
• delay control statement
• event control
• wait statement
• fork statement
• deassign statement
• force statement
• release statement

Unsupported operators

• Case equality and inequality operators (=== and !==)
• Division and modulus operators for variables

Unsupported gate-level constructs

• nmos,cmos, pmos, rnmos, rpmos, rcmos
• pullup, pulldown, tranif0, tranif1, rtran, rtainf0, and rtainf1 gate type signals

Miscellaneous constructs, such as hierarchical names within a module

Unsupported Simulation Directives

• 'accelerate
• 'celldefine
• 'default_nettype
• 'endcelldefine
• 'endprotect
• 'expand_vectornets
• 'noaccelerate
• 'noexpand_vectornets
• 'noremove_netnames
• 'nounconnected_drive
• 'protect
• 'remove_netnames
• 'resetall
• 'timescale
• 'unconnected_drive

VLSI Frequently Asked Interview Questions & Answers（part 4）

25. What is latchup in CMOS design and ways to prevent it?

To best understand the concept behind the latchup, we need to understand the concept behind SCR(Silicon Controlled Rectifiers), and how to model the basic transistor in an SCR structure and on what conditions SCR structures are created in the CMOS design process and its effects and what are the ways used to prevent it in the design-phase.An SCR is an acronym for Silicon Controlled Rectifier. It works similar to a typical diode, but is controlled similar to a bipolar transistor as far as connections go. Connection points are Anode [A], Cathode [K], and Gate [G]. The SCR is made up of two "P-N" junctions with a "Gate" attachment between them. The gate is connected between the two P-N junctions with a current waiting in the forward bias direction [+ to -] and the voltage is above 1-volt. A momentary pulse to the gate will cause the SCR to conduct and current will flow across the device until the value changes.

25. What are the various design changes you do to meet design power targets?

Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enable's gives a lot of power-savings. As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced. related information.

Calculate Depth of FIFO

It is an interesting Architectural decision, what should be our FIFO depth?

• What is the Transmitter data rate?
• What is the reciever data rate?

when there is a requirement for FIFO? when the Transmitter data rate and the recieve data rate are not in sync rather they dont match.The read is slower than the write, so there is always a chance the data will be lost, so FIFO will be an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss

Possible scenarioes:

Scenario 1:

Write is in maximum condition & Read is in minimum condition , means Write process is writing the data faster and read is reading or accessing the data slowest.

Scenario 2:

Whether the design supports only single writes or burst writes also. It becomes more complex when burst writes are present.

Scenario 3:

Write with no idle cycles and read with idle cycles.

Scenario 4:

Is the design's requirement is of Synchronous FIFO or an asynchronous FIFO?

Synchronous FIFO: A First In First Out memory, where in the has a control logic mechanism, has read and write pointers, generates Status signals and places handshake signals across. Sync FIFO has a same clock frequency for both read and write operation. The control/status signals could be Read Error, Write Error signals generated. Read Error generated when the FIFO is empty and Write Error is generated when the FIFO is full, writing may cause a data loss.Based on these signals can generate interrrupt signals to act upon. Handshake signals could be Read Enable or a Write Enable, Write Acknowledge and read acknowledge.

Asynchronous FIFO: The operation of Write and Read of a FIFO is purely asynchronous.

Scenario 5:

The Data width of an Tx and Rx are different.

Watermarks as Threshold setters

Set an low watermark and high watermark

Details about depth of FIFO

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system mainly depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.

For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.

So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.

So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

So following up with the equation as explained below:

Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).

Here we have not considered the synchronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.

Example : FIFO Depth Calculation

Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,

• A synchronized fifo
• Writing clock 30MHz - F1
• Reading clock 40MHz - F2
• Writing Burst Size - B
• Case 1 : There is 1 idle clock cycle for reading side - I
• Case 2 : There is 10 idle clock cycle for reading side – I

FIFO depth calculation = B - B *F2/(F1*I)

If we have alternate reading cycles, i.e. between two reading cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)

In our present problem FIFO depth = B - B *40/(30*2)= B(1-2/3)= B/3

That means if our Burst amount of data is 10, FIFO DEPTH = 10/3 = 3.333 = 4 (approximately)

If B = 20, and then FIFO depth = 20/3 = 6.6 = 7 or 8 (clocks are asynchronous)

If B = 30 FIFO depth = 30/3 = 10 or 11 (clocks are asynchronous)

If 10 IDLE cycles between two reading cycles .

FIFO DEPTH = B - B *F2/(F1*10) .

= B(1-4/30)

= B * 26 /30

Synopsys Synthesis Constraints Template

###Customize according to your Design needs

########################################################

#### Portion to Edit

#### Variables clock1_name is the Clock name, clock1_period is the Clock period,

#### clock1_period_half is the half of the clock period

#### set clock1_name

#### set clock1_period

#### set clock1_period_half [expr $clock1_period / 2]

#### set clock1_period_onetenth [expr $clock1_period / 10]

#### set clock1_period_onetwenth [expr $clock1_period / 20]

#### set clock1_latency

#### set CTS_clock1_skew

########################################################

#### Source the .synopsys_dc_setup file, File which has all the library settings

source .synopsys_dc_setup

#### Read the rtl files

read_verilog

### Similar way read all the RTL files

### Specify the Top-level file name

current_design

#### Link the design

link

#### Uniquify the design, for designs with multiple instantiation

uniquify

####Specify the Clocks in the Design ######

#### Example for one Clock in the Design named clock1

create_clock -period $clock1_period -waveform [list 0 $clock1_period_half ] -name $clock1_name

###

set_clock_skew -ideal -uncertainty $CTS_clock1_skew $clock1_name

set_clock_transition 0.3 $clock1_name

set_clock_latency $clock1_latency_number $clock1_name

set_dont_touch_network $clock1_name

#### Generate the same list of constraints for all the clocks in the design

#### Generate the False and Multi-cycle paths in the design as Timing Exceptions for the tool.

#### False And Multi-cycle paths are purely Design Specific.

#set_false_path -from -to -setup

#set_false_path -from -to -hold

#set_multicycle_path -from -to

##### Steps to constrain the inputs/outputs and the design

set_input_transition $clock1_period_onetenth [all_inputs]

set_max_transition $clock1_period_onetwenth $current_design

#### Specify the wire-load model

set auto_wire_load_selection true ### Tool automatically selects the wire-load model

#### Create virtual clocks to constrain the ports.To understand concept behind the virtual clocks

#### Check out the ASIC FAQ's column.

#### To constrain inputs

set_input_delay -clock

### Similar way define for all the inputs and w.r.t virtual clocks

#### To constrain out-puts

set_output_delay

-clock

### Similar way define for all the outputs and w.r.t virtual clocks

### To constrain purely combinational paths

set_max_delay -from -to

### For the high fanout nets for which tree will be built and to get away from false loading violation

set_ideal_net

set_ideal_net

### In-order to constrain specific paths passing through the muxes, for example for the tool to

### concentrate on the functional-paths , specify case_analysis for functional paths.

set_case_analysis

#### If the design requirement is for area critical designs

set_max_area 0

#### To prevent the tool from optimizing

#set_dont_touch

####Mapping the RTL specific to the Targetted Technology Library

#### The command means to map it , with scannable flop's, with high optimization possible,

#### Area optimized for non-critical-paths as-well-as boundary paths optimized.

compile -scan -map_effort high -area_effort high -boundary_optimization

#### Save the database

write -f db -h -o

#### Set some variables for proper saving of verilog netlist file

set verilogout_no_tri true

set bus_naming_style [format "%s%s" "%s\[" "%d\"]

write -f verilog -h -o

### Save the Used SDC(Synopsys Design Constraints file>

write_sdc

###Report Generation

report_constraints -all_violators -verbose ### Command to report all the violations

report_area ### command to report the design area

report_reference ### command to report the design details as per the sub-blocks

### A very powerful command to know the quality of the design constraints

check_design###Command to know the design

#### Now, let us know the Test Part of the Design

set test_default_period 100

set test_default_delay 5

set test_default_bidir_delay 30

set test_default_strobe 35

set test_default_strobe_width 0

#### Specify that there is no scan-chain present in the design

set_scan_configuration -existing_scan false

#### specify whether clock mixing is allowed or not while scanstitching

set_scan_configuration -clock_mixing no_mix

#### specify the style of flip-flop

set_scan_configuration -style multiplexed_flip_flop

#### Specify the scanchain methodology whether full-scan or partial scan

set_scan_configuration -methodology full_scan

#### Specify the longest chain length according to the tester memory

set_scan_configuration -longest_chain_length 200

#### Specify the scan-enable signal

set_scan_signal test_scan_enable -port

#### Specify a case analysis value for to the tool to be in the scan-mode while scan-stitching

set_test_hold

#### Specify the designs for which scan-stitching is not required

set_scan_element false [get_designs

#### Specify the scan-in and scan-out port of the design to the tool

set_scan_signal test_scan_in -port [get_ports

set_scan_signal test_scan_out -port [get_ports

#### specify the test-clock in the design

create_test_clock <> -period <> -waveform {rise-edge fall-edge}

#### run the check-test to know the design violations w.r.t. test

check_test -verbose

##### command to insert scan

insert_scan -map_effort high

#### Report generation

report_test -scan_path ### command to list all the scan-chains

#### Save the database

write -f db -h -o

#### Set some variables for proper saving of verilog netlist file

set verilogout_no_tri true

set bus_naming_style [format "%s%s" "%s\[" "%d\"]

write -f verilog -h -o

###Report Generation after scan-insertion

report_constraints -all_violators -verbose ### Command to report all the violations

report_area ### command to report the design area

report_reference ### command to report the design details as per the sub-blocks

Vim Study Book(part 2)--Cursor motion

Cursor motion

The mode

When you want to move the cursor, first go to command mode. Although you can use Ctrl combined keys to move the cursor in insert mode, they just inferior ways. I suggest never using Ctrl combined commands to move cursor. By all means, don't think about the arrow keys and the mouse when trying to move the cursor.

h j k l

h j k l are the four most basic cursor motion commands. You should use the index finger to press h and j, use your middle finger for k and your ring finger for l. These commands are designed for efficiency of your work and the comfort of your hand, but not so that you can do without learning. You should practice until they become of your instincts. Try open a file and use only your right hand to browse the whole file and move the cursor around, without looking at the keyboard. To practice effectively, never use the arrow keys and the mouse.

Faster

After you get used to h j k l, you may find these commands a bit slow. Yes, they are for short range movements. To move quickly, you need to learn other commands.

The w command moves cursor forward by a word, while b command moves cursor backward by a word. If you're locating a target in a single line, these two might be useful.

The 0 command moves the cursor to the beginning of the current line, while $ command moves the cursor to the end of the current line. The ^ command moves the cursor to the first non-blank character of the current line.

Even faster

If you want to go to the end of the file, press G. If you want to go to the beginning of the file, press 1G.

If you want to go to the nth line, type the number n followed by G. For example, 150G takes you to the 150th line. If you don't have as many as 150 lines, you won't be punished -- the cursor just jump to the last line.

There is an alternative command to jump to a line if you know its number. Type the colon character : followed by the line number and ENTER, such as :150. This has the same effect as the G command, but the advantage is that the colon and the line number you have typed are shown at the bottom of the screen.

But how do we know the number of a line? Usually we don't know. Therefore, usually we only use G and 1G, which take us to the end or the beginning of the file. Of course, you may have an estimate of the line number where you want to go. Then just go there and then use j k to adjust the cursor location further.

If you do want to use line numbers precisely, you can type :set number to let vim display line numbers on the screen. The line numbers on the screen are not part of your file and can be hidden by type :set nonumber.

A good place to use line numbers is when you compile and debug programs. The compiler usually report the number of the lines where errors occur. Using those numbers you can jump directly to the error spot.

Move by screen.
Press Ctrlf moves you forward by one screen of text, and Ctrlb moves you backward by one screen of text.

Ctrlf and Ctrlb are faster, but pressing Ctrl key can be tiring. To avoid that, you may use the following commands to map Space key and Backspace key to them respectively.

:map  
:map  

Move to the matched bracket
The % command is a special cursor motion command. When the cursor is at any one of the bracket characters ( ) [ ] { }, hitting the % takes the cursor to its match, if there is one. If you're a C programmer, you'll find this very useful.

Know what you really want

Sometimes what you want to do is not just moving cursor. Then perhaps there is a command which combines your desired cursor motion and your other intention. For example, you may try to move the cursor to the right by l and then press i to insert. But that two operations is what the command a for. You may want to move cursor to the end of the line by $ and then use a to enter insert mode, but you can do it by one command A.

There are a lot of editing commands which combine cursor motions with other functions such as a A I o O cw C s. Try using them instead of doing two the things separately.

Move cursor by searching a pattern

Sometimes you don't know where your target is, but you know what your target is. Then don't browse the file from start to end, word by word. That is harmful to your eyes. Try searching the word or the pattern using the slash command /. For example, you want to move the cursor the word target, you can type

/target

Then the cursor will jump to the first occurrence of target. If this target is not your target, just keep pressing

n

to go to subsequent occurrences of the word target untill you find your target.

Search is the most effective and fastest way of moving the cursor and locating the target, especially when you're doing things like writing HTML documents or LaTeX source files. The formatted documents are shown in one window, where the source files are edited by vim. When you watch the formatted documents and spot some problems, remember a couple of words from the place. Then go to the source file search these words to find the place.

When you edit large files, you can insert some location tags which can help you navigate through the file easily. For example, in a LaTeX file, you may insert comments like %Section 1 and %Section 2. Whenever you want to go to the start of Section 1, type

/Section 1

Move cursor by searching a character

Search a character within the line. The f and F commands can be used to move cursor quickly. To move the cursor to the first occurrence of a character c in the current line

fc

To go to the first occurrence of a character c in the left

Fc

If one fc didn't take the cursor to the desired place and you need to repeat the search, remember that instead of doing fc again, you can use the semicolon command to repeat the last fc or Fc search

;

in the same direction, and use the comma command

,

to do it in the opposite direction. This can be very handy since the semicolon and comma keys are very easy to hit.

VLSI Frequently Asked Interview Questions & Answers（part 3）

15. What are the various yield-losses in the design?

The yield loss in the design is characterized by

1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens)

2. Parametric yield losses, due to process variations.

16. what is meant by virtual clock definition and why do i need it?

Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads are passing the data.

For Further Understanding of the concept. http://www.vlsichipdesign.com/images/virtual_clock.jpg

17. What are the various Design constraints used while performing Synthesis for a design?

1. Create the clocks (frequency, duty-cycle).

2. Define the transition-time requirements for the input-ports.

3. Specify the load values for the output ports

4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip.

5. Specify the case-setting (in case of a mux) to report the timing to a specific paths.

6. Specify the false-paths in the design

7. Specify the multi-cycle paths in the design.

8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold).

18. Specify few verilog constructs which are not supported by the synthesis tool.

initial, delays, real, force and release, fork join.

19. What are the various Variations which impacts timing of the design?

20.what are the various capacitances with an MOSFET?/strong>

21.Vds-Ids curve for an MOSFET, with increasing Vgs.

22. Basic Operation of an MOSFET.

23. What is Channel length Modulation?

24. what is body effect?

Increase in Vt(threshold voltage) , due to increase in Vs(voltage at source), is called as

body effect.

VLSI Frequently Asked Interview Questions & Answers（part 2）

7. What is High-Vt and Low-Vt cells.

Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices which have less delay but leakage is high. The thereshold(t) vloltage dictates the transistor switching speed , it matters how much minimum threshold voltage applied can make the transistor switching to active state which results to how fast we can switch the trasistor. disadvantage is it needs to maintain the transistor in a minimum subthreshold voltage level to make ir switch fast so it leads to leakage of current inturn loss of power.

8. What is LEF mean?

LEF is an ASCII data format from Cadence Design inc, to describe a standard cell library. It includes the design rules for routing and the Abstract layout of the cells. LEF file contains the following,

Technology: layer, design rules, via-definitions, metal-capacitance

Site : Site extension

Macros : cell descriptions, cell dimensions, layout of pins and blockages, capacitances

To get further insight to the topic, please check this http://www.csee.umbc.edu/~cpatel2/links/414/slides/lect03_LEF.pdf

9. what is DEF mean?

DEF is an ASCII data format from Cadence Design inc., to describe Design related information.

10. Steps involved in designing an optimal padring

1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less .

2. Ensure that the Padring ful-fills the ESD requirement, Identifyh the power-domains, split the domains, Ensure common ground across all the domains.

3. Ensure the padring has ful-filled the SSN(Simultaneous Switching Noise) requirement.

4. Placing Transfer-cell Pads in the cross power-domains, for different height pads, to have rail connectivity.

5. Ensure that the design has sufficient core power-pads.

6. Choose the Drive-strenght of the pads based on the current requirements, timing.

7. Ensure that there is seperate analog ground and power pads.

8. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O's.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs float.

9. Ensure that oscillator-pads are used for clock inputs.

10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength.

11. Breaker-pads are used to break the power-ring, and to isolate the power-structure across the pads.

12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin.

13. In case if required , place pads with capacitance.

11. What is metastability and steps to prevent it.

Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously.

Steps to prevent Metastability.

1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event.

2. Use synchronizers between cross-clocking domains to reduce the possibility from metastability.

3. Using Faster flip-flops (which has narrower Metastable Window).

12. what is local-skew, global-skew,useful-skew mean?

Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

13. What are the various timing-paths which i should take care in my STA runs?

1. Timing path starting from an input-port and ending at the output port(purely combinational path).

2. Timing path starting from an input-port and ending at the register.

3. Timing path starting from an Register and ending at the output-port.

4. Timing path starting from an register and ending at the register.

14. What are the various components of Leakage-power?

1. sub-threshold leakage

-courtesy Khondker

2. gate leakage

-courtesy Khondker

3. reverse biased drain substrate and drain substrate junction band-band tunnelling