VLSI Frequently Asked Interview Questions & Answers（part 4）

25. What is latchup in CMOS design and ways to prevent it?

To best understand the concept behind the latchup, we need to understand the concept behind SCR(Silicon Controlled Rectifiers), and how to model the basic transistor in an SCR structure and on what conditions SCR structures are created in the CMOS design process and its effects and what are the ways used to prevent it in the design-phase.An SCR is an acronym for Silicon Controlled Rectifier. It works similar to a typical diode, but is controlled similar to a bipolar transistor as far as connections go. Connection points are Anode [A], Cathode [K], and Gate [G]. The SCR is made up of two "P-N" junctions with a "Gate" attachment between them. The gate is connected between the two P-N junctions with a current waiting in the forward bias direction [+ to -] and the voltage is above 1-volt. A momentary pulse to the gate will cause the SCR to conduct and current will flow across the device until the value changes.

25. What are the various design changes you do to meet design power targets?

Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enable's gives a lot of power-savings. As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced. related information.