VLSI Frequently Asked Interview Questions & Answers（part 3）

15. What are the various yield-losses in the design?

The yield loss in the design is characterized by

1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens)

2. Parametric yield losses, due to process variations.

16. what is meant by virtual clock definition and why do i need it?

Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads are passing the data.

For Further Understanding of the concept. http://www.vlsichipdesign.com/images/virtual_clock.jpg

17. What are the various Design constraints used while performing Synthesis for a design?

1. Create the clocks (frequency, duty-cycle).

2. Define the transition-time requirements for the input-ports.

3. Specify the load values for the output ports

4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip.

5. Specify the case-setting (in case of a mux) to report the timing to a specific paths.

6. Specify the false-paths in the design

7. Specify the multi-cycle paths in the design.

8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold).

18. Specify few verilog constructs which are not supported by the synthesis tool.

initial, delays, real, force and release, fork join.

19. What are the various Variations which impacts timing of the design?

20.what are the various capacitances with an MOSFET?/strong>

21.Vds-Ids curve for an MOSFET, with increasing Vgs.

22. Basic Operation of an MOSFET.

23. What is Channel length Modulation?

24. what is body effect?

Increase in Vt(threshold voltage) , due to increase in Vs(voltage at source), is called as

body effect.