DC & PhyC .synopsys_dc.setup file
set search_path [list . /usr/golden/library/std_cells]
settarget_library [list ex25_worst.db]
setlink_library "*, ex25_worst.db ex25_best.db"
setsymbol_library [list ex25.sdb]
setphysical_library[list ex25_worst.pdb]
define_name_rules BORG–allowed {A-Za-z0-9_} –first_restricted “_” –last_restricted “_” -max_length 30 –map {{“*cell*”, “mycell”}, {“*–return”, “myreturn”}}
set bus_naming_style %s[%d]
set verilogout_no_tri true
set verilogout_show_unconnected_pins true
set test_default_scan_style multiplexed_flip_flop
Labels: ASIC/IC Studybook
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