verification coding style

1)Fork --- join
module inline_tb;
//declare variables
//instantiate designs
initial begin
initialize_design;
fork
monitor_data;
monitor_error;
monitor_timeout;
run_test;
join
end
endmodule
Note: fork-join can be implemented in the begin-end block.
2 Stimulus From Loops

initial begin
for (i = 0;i <= 255;i=i + 1）
@(negedge clk) stimulus = i;
#20 $finish;
end
3 readmemb & readmemh
TestBench作相应的定义：
Reg [7:0] A, B;
Reg Start;
……
Reg [33:0] Vector, Test_Vector[0:Test_Length];
…….
$readmemb(“Test_Fixed.v”, Test_Vector);
……
For (I=0; I 按一定时序将Test_Vector[I]送入Vector并送入A、B、Start；