Systemverilog Tutorial(Ch1-intorduction)

Today is the first day of 2008!

Happy New Year For Everyone!

Now Let us make a closed study on the systemverilog.

Several days ago, I came acrossed a book called "Systemverilog Assertion". The preface of the book intrigues my interest on Systemverilog that may be the next generation hardware description language. It is reported that the systemverilog has fixed its roots steadily in EDA field such as system design and verifications of ASIC/IC design.

So it is necessary for us to make a acquaintance with it. Now I have googled many resources about it and sort them as follows step by step! Just follow me! Be patient and systemverilog world is coming.

The following chapter is about the introductions of systemverilog.

		Introduction
		Verilog 1995 version has been in market for a very long time. IEEE extended the features of Verilog 1995 and released it as Verilog 2001. But this was no good for verification engineers, so verifcation engineers had to use languages like "e", VERA, Testbuider. It was rather painfull to have two language, one for design and other for verification. SystemVerilog combines the Verification capabilties of HVL (Hardware Verification Language) with ease of Verilog to provide a single platform for both design and verification.
		Some of the new features in SystemVerilog are as listed below.
		C type data types like int, typedef, struct, union, enum. Dynamic data types : struct, classes, dynamic queues, dynamic arrays. New operators and built in methods. Enhanced flow control like, foreach, return, break, continue. Semaphores, mailboxes, event extensions. classes for object oriented programming. Assertions. Coverage. VPI extensions.
		Now IEEE has accepted the SystemVerilog, and it is called 1800-2005 standard.
		Anyone with background of C++, or OO programming language will feel at home with SystemVerilog. But on other hand if you have been thinking C or C++ is not required, then you may be shocked to know that SystemVerilog is very much like C++.