Lubee's Blog--Digtial IC Fan's Home: Calculate Depth of FIFO

It is an interesting Architectural decision, what should be our FIFO depth?

What is the Transmitter data rate?
What is the reciever data rate?

when there is a requirement for FIFO? when the Transmitter data rate and the recieve data rate are not in sync rather they dont match.The read is slower than the write, so there is always a chance the data will be lost, so FIFO will be an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss

Possible scenarioes:

Scenario 1:

Write is in maximum condition & Read is in minimum condition , means Write process is writing the data faster and read is reading or accessing the data slowest.

Scenario 2:

Whether the design supports only single writes or burst writes also. It becomes more complex when burst writes are present.

Scenario 3:

Write with no idle cycles and read with idle cycles.

Scenario 4:

Is the design's requirement is of Synchronous FIFO or an asynchronous FIFO?

Synchronous FIFO: A First In First Out memory, where in the has a control logic mechanism, has read and write pointers, generates Status signals and places handshake signals across. Sync FIFO has a same clock frequency for both read and write operation. The control/status signals could be Read Error, Write Error signals generated. Read Error generated when the FIFO is empty and Write Error is generated when the FIFO is full, writing may cause a data loss.Based on these signals can generate interrrupt signals to act upon. Handshake signals could be Read Enable or a Write Enable, Write Acknowledge and read acknowledge.

Asynchronous FIFO: The operation of Write and Read of a FIFO is purely asynchronous.

Scenario 5:

The Data width of an Tx and Rx are different.

Watermarks as Threshold setters

Set an low watermark and high watermark

Details about depth of FIFO

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system mainly depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.

For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.

So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.

So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

So following up with the equation as explained below:

Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).

Here we have not considered the synchronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.

Example : FIFO Depth Calculation