VLSI Frequently Asked Interview Questions & Answers

1. what is the difference between mealy and moore state-machines

In the mealy state machine we can calculate the next state and output both from the input and state. But in the moore state machine we can calculate only next state but not output
from the input and state and the output is issued according to next state.

2. How to solve setup & Hold violations in the design

To solve setup violation

1. optimizing/restructuring combination logic between the flops.
2. Tweak(To adjust; fine-tune) flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations.
4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)

To solve Hold Violations

1. Adding delay/buffer[as buffer offers lesser delay, we go for spl
Delay cells whose functionality Y=A, but with more delay]

2. Making the launch flop clock reaching delayed

3. Also, one can add lockup-latches [in cases where the hold time
requirement is very huge, basically to avoid data slip]

3. What is antenna Violation & ways to prevent it

During the process of plasma etching(等离子腐蚀), charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation.

The ways to prevent is , by making jogging the metal line, which is at least one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect.

Another way of preventing is adding reverse Diodes at the gates

4. We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we don't write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a module will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the logic , structure and map it to the library cells, so we use a command in synthesis , called as "UNIQUIFY" which will replace the instantiations with the real logic, because once we are in a synthesis stages we have to visualize as real cells and no more modelling just for functionality alone, we need to visualize in-terms of physical world as well.

5. what is tie-high and tie-low cells and where it is used

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which wants Vss connects itself to Tie-low.

6. what is the difference between latches and flip-flops based designs

Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex.