Cadence NC simulator teaching<2>_hdl.var Setting
1.The hdl.var File
The hdl.var file is an optional configuration file. This ASCII text file can contain: Configuration variables, which determine how your design environment is configured.
These include:
1. Variables that you can use to specify the work library where the compiler stores compiled objects and other derived data. For Verilog, you can use the LIB_MAP or WORK variables. For VHDL, use the WORK variable.
2. For Verilog, variables (LIB_MAP, VIEW_MAP, WORK) that you can use to specify the
libraries and views to search when the elaborator resolves instances. Variables that allow you to define compiler, elaborator, and simulator command-line options and arguments. Variables that specify the locations of support files and invocation scripts.
You can have more than one hdl.var file. For example, you can have a project hdl.var file that contains variable settings used to support all your projects and you can have local hdl.var files located in specific design directories that contain variable settings specific to each project, such as the setting for the WORK variable.
If you define the same variable in more than one file, the last variable read is used. For example, suppose that you have the following hdl.var file in your current working directory.
The VERILOG_SUFFIX variable defines recognized file extensions for Verilog source files.
INCLUDE ~/hdl.var
DEFINE VERILOG_SUFFIX (.ver)
DEFINE WORK ./worklib
The hdl.var file in your home directory is as follows:
DEFINE VERILOG_SUFFIX (.vg)
The first line in the hdl.var file includes the hdl.var file in your home directory. This file sets the VERILOG_SUFFIX variable to .vg. The next line then sets the same variable to .ver. Only this suffix (.ver) will be recognized as a valid suffix.
Now, suppose that the hdl.var file was written as follows:
DEFINE VERILOG_SUFFIX (.ver)
INCLUDE ~/hdl.var
DEFINE WORK ./worklib
Inthiscase, the VERILOG_SUFFIX variable is first set to .ver, and then redefined to be .vg. Only the .vg suffix will be recognized.
If you want both suffixes to be recognized, you could, for example, do the following:
# ./hdl.var
INCLUDE ~/hdl.var
DEFINE VERILOG_SUFFIX $VERILOG_SUFFIX (.ver)
DEFINE WORK worklib
# ~/hdl.var
DEFINE VERILOG_SUFFIX (.vg)
In this case, VERILOG_SUFFIX is first set to .vg. Then the .ver suffix is appended to this
definition so that the compiler will recognize both suffixes.
1.1 DEFINE variablevalue
Defines a variable and assigns a value to the variable.
The following example defines the variable WORK to be worklib.
DEFINE WORK worklib
The following example defines VERILOG_SUFFIX as the list .v, .vg, and .vb.
DEFINE VERILOG_SUFFIX (.v, .vg, .vb)
The following example defines the variable NCVLOGOPTS, which is used to specify command-line options for the ncvlog compiler.
DEFINE NCVLOGOPTS -messages -errormax 10 –update
1.2 UNDEFINE variable
Causes variable to become undefined. This statement is useful for removing definitions
That were defined in other files. If variable was not previously defined, you will not get an error message.
UNDEFINE NCUSE5X
1.3 INCLUDE filename
Reads filename as an hdl.var file.
Use INCLUDEE to include the variable definitions contained in the specified file. The pathname can be absolute or relative. If it is relative, it is relative to the hdl.var file in which it is defined.
Examples:
INCLUDE ~/my_hdl.var
INCLUDE /users/${USER}/hdl.var
1.4 Example hdl.var File
# Define the work library
DEFINE WORK worklib
# Define valid Verilog file extensions
DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg)
# Define valid VHDL file extensions
DEFINE VHDL_SUFFIX (.vhd, .vhdl)
# Specify command-line options for the ncvhdl compiler
DEFINE NCVHDLOPTS -messages -errormax 10
# Specify command-line options for the ncvlog compiler
DEFINE NCVLOGOPTS -messages -errormax 10 -ieee1364
# Specify command-line options for the elaborator
DEFINE NCELABOPTS -messages -errormax 10 -ieee1364 -plinooptwarn
# Specify the simulation startup command file
DEFINE NCSIMRC /usr/design/simrc.cmd
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