Debugging you design with Simvision

Simvision is a unified graphical debugging environment for Cadence simulators. It can be used for viewing waveform, watching source code, and tracing driver or load.
In order to debugging design with Simvision, firstly we need dump waveform in SHM format, and then use Simvision to analyze waveform and design.

1. Dump waveform in SHM format with NC simulator

In order to dump waveform in SHM format with NC simulator, you should prepare a .tcl file, and use it as input when do ncsim, that is: ncsim –input xx.tcl …………….

Here is an example of .tcl file:
run 100000ns
database -open waves -into waves.shm –default -event //create database waves.shm
probe -create top -depth to_cell -tasks -functions -all -database waves –name proaa //create probe proaa, which specify download all signals(except memories) in scope top into waves.shm
run 50000ns
probe –disable proaa //disable probe proaa, stop dump waveform
run 200000ns
exit
In above example (assume that above .tcl file named ncsim.tcl), ncsim.tcl specify dumping waveform from 100000ns to 150000ns, and dumping all signals (except memories) in scope top into waves.shm.

For more detailed information about these command, please execute /cad/ldv5.4s011/tools.lnx86/bin/cdsdoc, open NC-Verilog, then open NC-Verilog simulator help, and then open 12.using TCL command – line interface. Or you can refer to /logic/judylu/simulator_commands.html#1042397.

2. Debugging design with SHM and NC snapshot

After simulation finish, you can debug design with Simvision.
If you have specify dump waveform, you will find there is a directory named *.shm (such as waves.shm). In this directory, there are 2 files, the one is *.trn, the other is *.dsn. The former stores signal values, and the latter stores other design information.

First start Simvision, and then open database such as waves.shm/waves.trn. Then you can view the waveform dumped. If you want to view source code or you want to do trace, Simvision will load the snapshot automatically. So if you want to view source code or you want to do trace, you can not delete you library.

You can find Simvision user guide at cdsdoc: NC-Verilog: Simvision User Guide.

Lost: Season 5 prediction

Season 4 just ended and most of us will have to wait till January 2009 to see the new episodes. Till then the team behind Lost are planning to keep us busy and baffled with the islands mysteries with more hidden clues.

Starting from Season’s 4 last episode, during the commercial break a strange advert was aired. A company called Octagon Global Recruiting was advertising job openings/recruitment that will take place in San Diego, California on the 24th of July. On the Octagon web site it clearly links the new company with the Dharma Initiative and its purpose will probably be revealed during the ComiCon conference that will take place in San Diego on that day.


Fans of ABC's Lost may recall hearing that Carlton Cuse and Damon Lindelof demanded from the network that an end date be set for the series so they could properly map out the upcoming episodes and seasons and conclude the show in a satisfying way (for them, maybe not for us fans). Well, according to E! Online, ABC will soon announce that Lost will conclude at the end of Season 5 (we're currently in season 3).

Some fans may think this is bad news but if you take time to analyze it, you'll see it is a good thing. Producers and writers now have the assurance that ABC will air the show for two more seasons, nothing more and... nothing less. This means that they can plan the storylines and reveals accordingly. And, hopefully for us, they can plan a proper series finale instead of planning a "season finale that could serve as a series finale" or just leave us hanging with tons of cliffhangers and no more episodes to answer the questions.

The network is also rumored to confirm this report that Lost will air from January to May starting next year so that episodes air in a back-to-back fashion à la 24. The last news ABC is set to announce about the series' schedule is that it will more than likely go back to its original time: 9 p.m. Expect these announcements to be made during ABC's Upfront presentation on May 15.

Differences between Tasks and Functions

Tasks and functions serve different purposes in Verilog. We discuss tasks and functions in greater detail in the following sections. However, first it is important to understand differences between tasks and functions, as outlined in the following.

A function can enable another function but not another task.
A task can enable other tasks and functions.

Functions always execute in 0 simulation time.
Tasks may execute in non-zero simulation time.

Functions must not contain any delay, event, or timing control statements.
Tasks may contain delay, event, or timing control statements.

Functions must have at least one input argument. They can have more than one input.
Tasks may have zero or more arguments of type input, output, or inout.

Functions always return a single value. They cannot have output or inout arguments.
Tasks do not return with a value, but can pass multiple values through output and inout arguments.



Both tasks and functions must be defined in a module and are local to the module. Tasks are used for common Verilog code that contains delays, timing, event constructs, or multiple output arguments. Functions are used when common Verilog code is purely combinational, executes in zero simulation time, and provides exactly one output. Functions are typically used for conversions and commonly used calculations.

Tasks can have input, output, and inout arguments; functions can have input arguments. In addition, they can have local variables, registers, time variables, integers, real, or events. Tasks or functions cannot have wires. Tasks and functions contain behavioral statements only. Tasks and functions do not contain always or initial statements but are called from always blocks, initial blocks, or other tasks and functions.

$test$plusagrs systme function in verilog-2001

Verilog allows users to create new simulation invocation options.

The $test$plusargs system function checks to see if a “plus” option was used when simulation was invoked.

Example : NCverilog test.vchip.v +test2

Pattern file code can be writen as the followings:

initial
begin
if($test$plusargs(“test1”))
$readmemh(“test1.dat”,vectors);
elseif($test$plusargs(“test2”))
$readmemh(“test2.dat”,vectors);
elseif($test$plusargs(“test3”))
$readmemh(“test3.dat”,vectors);
else $display(“Error:notestoptionspecified”);
end

Incisive verification--NC commands

ncvlog
ncvlog [options] source_file ...

Options:
-DEFINE -- Defines a macro
-FILE -- Load command line arguments from rmation
-MESSAGES -- Specifies printing of informative messages
-NOCOPYRIGHT -- Suppresses printing of copyright banner
-NOSTDOUT -- Turn off output to screen
-NOWARN -- Disables printing of the specified warning message

Examples:
-- To compile all the modules in source.v
% ncvlog source.v

-- To compile with informative messages
% ncvlog -messages source.v

2. ncelab
ncelab [options] [lib.]cell[:view]

Options:
-MESSAGES -- Specifies printing of informative messages
-NOCOPYRIGHT -- Suppresses printing of copyright banner
-NOSTDOUT -- Turn off output to screen
-TIMESCALE -- Set default timescale on Verilog modules.
-ACCESS -- Set default access visibility. {+rwc} turn on read/write/connectivity.
-FILE -- Load command line arguments from
-LOADPLI1 -- Specify the library_name:boot_routine(s) to dynamically load a PLI1.0 application
-MAXDELAYS -- Selects maximum delays for simulation
-MINDELAYS -- Selects minimum delays for simulation
-TYPDELAYS -- Selects typical delays for simulation
-NONEG_TCHK -- Disallow negative values in SETUPHOLD & RECREM timing checks
-NONOTIFIER -- Notifiers are ignored in timing checks.
-NOSPECIFY -- Don't execute timing checks, ignore path delays and skip SDF annotations.
-NOTIMINGCHECKS -- Don't execute timing checks
-NOWARN -- Disables printing of the specified warning message
-NO_TCHK_MSG -- Turn off timing check warnings
-SDF_NO_WARNINGS -- Do not report SDF warnings

Examples:
-- To elaborate my_lib.top:behav
% ncelab my_lib.top:behav
% ncelab my_lib.top
% ncelab top

-- To elaborate with informative messages
% ncelab -messages my_lib.top:behav

3. ncsim
ncsim [options] [lib.]cell[:view]

Options:
-FILE -- Load command line arguments from
-GUI -- Enter window mode before running simulation
-INPUT -- Script to be executed during initialization
-MESSAGES -- Specifies printing of informative messages
-NOCOPYRIGHT -- Suppresses printing of copyright banner
-NONTCGLITCH -- Suppress delayed net glitch suppression messages
-NOSTDOUT -- Turn off output to screen
-NOWARN -- Disables printing of the specified warning message
-SDF_NO_WARNINGS -- Do not report SDF warnings

Examples:
-- To simulate the snapshot my_lib.top:snap
% ncsim my_lib.top:snap
% ncsim my_lib.top
% ncsim top

-- To simulate while writing to the log file ./ncsim.log
% ncsim -log ./ncsim.log my_lib.top:snap

-- To update the snapshot my_lib.top:snap and simulate
% ncsim -update my_lib.top:snap

4. ncverilog
ncverilog [all valid Verilog-XL arguments]

Supported Dash options:
-f Read host command arguments from file

Supported plus options:
+access+ Turn on Read, Write and/or Connectivity Access
+define+ Define a macro from commandline
+loadpli1= Specify the library_name:boot_routine(s) to dynamically load a PLI1.0 application from commandline
+maxdelays Selects maximum delays for simulation
+mindelays Selects minimum delays for simulation
+typdelays Selects typical delays for simulation
+ncdumpports_format+ Specify EVCD format flag for $dumpports
+neg_tchk Allow negative values in SETUPHOLD & RECREM timing checks (default)
+noneg_tchk Disallow negative values in SETUPHOLD & RECREM timing checks
+nocopyright Suppresses printing of copyright banner
+no_notifier Notifiers are ignored in timing checks
+nosdfwarn Do not report SDF warnings
+nospecify Suppresses timing checks and path delays in specify blocks.
Ignore SDF annotations.
+nostdout Turn off output to screen(terminal)
+notchkmsg Turn off timing check warnings
+notimingcheck Don't execute timing checks
+nowarn+ Disables printing of the specified warning message
+sdf_nowarnings Do not report SDF warnings

5. ncsdfc
ncsdfc [options] sdf_file

Options:
-COMPILE -- Compile the specified SDF files (default)
-DECOMPILE -- Decompile the specified SDF files
-LOGFILE -- Specifies the file to contain log information
-MESSAGES -- Specifies printing of informative messages
-NOCOPYRIGHT -- Suppresses printing of copyright banner
-OUTPUT -- Redirects compiled SDF output to the specified file
-WORSTCASE_ROUNDING -- Truncate min delays, round max delays up

Examples:
-- To compile an SDF file:
% ncsdfc dcache.sdf
Creates compiled SDF file dcache.sdf.X
-- To specify a name for the compiled SDF file:
% ncsdfc ipipe.sdf -OUTPUT ipipe.compiled
Creates compiled SDF file ipipe.compiled
-- To decompile a compiled SDF file:
% ncsdf -DECOMPILE ebox.sdf.X
Creates decompiled SDF file ebox.sdf.X.sdfd
-- To specify a name for the decompiled SDF file:
% ncsdfc -DECOMPILE ebox.sdf.X -OUTPUT ebox.sdfd
Creates decompiled SDF file ebox.sdfd

6. nchelp
nchelp [options] tool error
nchelp [-cdslib | -hdlvar]

Examples:
-- To find help on the error CUVWSP from ncelab
% nchelp ncelab CUVWSP

-- To find help on the error BADCLP from ncvlog
% nchelp ncvlog BADCLP

-- To list the currently defined libraries
% nchelp -cdslib

-- To list the currently supported tools
% nchelp -tools

-- To list the help for all supported tools with the BADCLP mnemonic
% nchelp -all BADCLP

What is MPW in ASIC filed?

The lasted news：
多项目晶圆（Multi Project Wafer，简称MPW）就是将多个具有相同工艺的集成电路设计放在同一晶圆片上流片，流片后，每个设计品种可以得到数十片芯片样品，这一数量对于设计开发阶段的实验、测试已经足够。而实验费用就由所有参加MPW的项目按照芯片面积分摊。实际成本仅为原来的5%-10%，极大地降低了培养集成电路研发阶段的费用门槛，也为集成电路设计师的大胆创新提供了一个宽松的设计环境，有效地推动了集成电路的发展。

开展MPW服务的创意最早出自美国，叫做MOSIS(MOS Implementation Service)。美国国防部军用先进研究项目管理局（DARPA）于1980年在其所属的研究院内建立了第一个非赢利的MPW加工服务机构MOSIS，主要是为军用集成电路服务。1985年，DARPA与NSF(National Science Foundation)把这一服务向美国大学集成电路设计课程的教学实验开放。1986年，这一服务进一步向企业界开放。到了1995年，美国以外的教学机构和企业也可以参加MOSIS组织的流片服务。据不完全统计，MOSIS自建立以来已经为超过45000个的集成电路设计项目提供了MPW流片服务。

目前，不少国家和地区都已建立了类似的服务机构，如欧洲的EUROPRACTICE、法国的CMP、韩国的IDEC、日本的VDEC、加拿大的CMC、台湾的CIC等，这些机构专门研究和处理专用集成电路设计付诸工艺流片过程中所遇到的问题。它们的工作包括面向工艺厂家和ASIC设计两个方面：对工艺厂家的工作主要是：规范各个集成电路厂家的工艺，制定内容统一、技术先进，且为各工艺厂家接受的设计规则，并将其提供给准备进行工艺流片的ASIC设计师；对 ASIC设计师的主要工作是：制定各类标准加工框架结构，对各个项目的设计芯片进行整合，统一加工，达到降低研制费用，加快研制过程的目的，同时也充分发挥了工艺线的能力，提高了设计水平，推动了新品研制。

世界上在集成电路研究开发方面领先的国家与地区，先后于80-90年代建立并实施了大规模的MPW计划，由此培育了众多的中小集成电路设计企业，培养了大批集成电路设计力量，完成了大量集成电路设计项目的开发工作。

近几年来，借鉴国外的先进经验，国内民用集成电路的MPW服务已经开展起来，如复旦大学、上海集成电路设计研究中心（ICC）、南京东南大学、清华大学、北京大学都已经开展了MPW服务，收到了较好的效果，促进了我国IC设计产业的发展。



Tape out 中文可翻译为“出带”，即：当你的设计完成，将最后的数据（GDSII）送出去给Foundry进行流片。通常，如果你是做“MPW”，当然是 Tape out 数据去MPW；MPW成功后，要量产，你的项目就单独去做Masks了，此时一般就不叫Tape out，只是生产安排。

来自凯明员工的信--当今3G芯片厂商的现状

转自http://tech.163.com/08/0508/11/4BDT4IUO000915BE.html
以下为信件原文：

随着员工欠薪事件的逐步解决，凯明后续的生存和发展问题就显得很突出了，实际上，我们也没有一个很清晰的思路。也许大多数人都离职了，寻找新的工作去了。凯明发展到这个地步，是很让人痛心的。

很感谢各位深夜还在董事会会议室外面陪伴我们的各位朋友，亏欠大家很多。也不胜感激。我尽可能写一些有价值的东西给大家。

我这几天深陷员工欠薪补偿的利益纠葛，不同的人的人性在这个时候表现出来，有些人只会索取和要求别人，有些人自觉帮助我们做一些事情，我们尽可能去平息不必要的争端。耗费了很多精力。昨天很晚了，我们几个员工代表出去吃饭，心情很郁闷，给大家争取了很多利益，还被人不理解。

TD产业发展到今天，隐患还是很大，信心问题、资金问题还是没有根本解决，这么下去很危险，凯明220多个受伤害的人，很多人也许就离开这个产业了，当然也会有一些人坚持下去。

TD的演进上，资金问题也会隐患很大，如果不解决这个问题，最终还是会沦为替国际大芯片公司打工的地步，我们自己的企业还是培养不起来。

海外战略投资者（TI、NXP、Nokia、Samsung等）在TD持续多年的投入，没有回报，6年是极限了，Maxim从TD RF首先撤退，更多国际大佬对TD采取观望态度。芯片和手机环节极度缺钱，投入巨大，风险极高。政府单靠扶持一个大唐是远远不够的。产业有自己的发展规律，特别是无线通信基带和射频芯片，投入大，周期长，失败率也高。没有一个乐观的市场前景和预期，大佬们谁敢轻易投资？玩家越来越少的时候，这个产业的危险性就越来越高了。

其他2G/3G技术上，华为在海思上烧了很多年了，海思离成功也还是很远，中兴也在做基带芯片，也不怎么的，大家都要交几年学费。Coolsand快倒闭了。

台湾的无线基带芯片公司也不少，但只有MTK成为主流芯片供应商，威盛走的是偏门（CDMA），Sunplus无线这块还没有大规模商用。

全球来看，整合大潮兴起，意法都收购了80%的NXP股份，估计今年还会有进一步力度很大的整合，包括基带芯片公司收购射频芯片公司等。

LTE方面，做TD的这些企业可能一时半刻是没有钱和资源来做了，国际巨头才有资格做的。

Cadence NC simulator teaching<2>_hdl.var Setting

1．The hdl.var File

The hdl.var file is an optional configuration file. This ASCII text file can contain: Configuration variables, which determine how your design environment is configured.

These include:

1． Variables that you can use to specify the work library where the compiler stores compiled objects and other derived data. For Verilog, you can use the LIB_MAP or WORK variables. For VHDL, use the WORK variable.

2． For Verilog, variables (LIB_MAP, VIEW_MAP, WORK) that you can use to specify the

libraries and views to search when the elaborator resolves instances. Variables that allow you to define compiler, elaborator, and simulator command-line options and arguments. Variables that specify the locations of support files and invocation scripts.

You can have more than one hdl.var file. For example, you can have a project hdl.var file that contains variable settings used to support all your projects and you can have local hdl.var files located in specific design directories that contain variable settings specific to each project, such as the setting for the WORK variable.

If you define the same variable in more than one file, the last variable read is used. For example, suppose that you have the following hdl.var file in your current working directory.

The VERILOG_SUFFIX variable defines recognized file extensions for Verilog source files.

INCLUDE ~/hdl.var

DEFINE VERILOG_SUFFIX (.ver)

DEFINE WORK ./worklib

The hdl.var file in your home directory is as follows:

DEFINE VERILOG_SUFFIX (.vg)

The first line in the hdl.var file includes the hdl.var file in your home directory. This file sets the VERILOG_SUFFIX variable to .vg. The next line then sets the same variable to .ver. Only this suffix (.ver) will be recognized as a valid suffix.

Now, suppose that the hdl.var file was written as follows:

DEFINE VERILOG_SUFFIX (.ver)

INCLUDE ~/hdl.var

DEFINE WORK ./worklib

Inthiscase, the VERILOG_SUFFIX variable is first set to .ver, and then redefined to be .vg. Only the .vg suffix will be recognized.

If you want both suffixes to be recognized, you could, for example, do the following:

# ./hdl.var

INCLUDE ~/hdl.var

DEFINE VERILOG_SUFFIX $VERILOG_SUFFIX (.ver)

DEFINE WORK worklib

# ~/hdl.var

DEFINE VERILOG_SUFFIX (.vg)

In this case, VERILOG_SUFFIX is first set to .vg. Then the .ver suffix is appended to this

definition so that the compiler will recognize both suffixes.

1．1 DEFINE variablevalue

Defines a variable and assigns a value to the variable.

The following example defines the variable WORK to be worklib.

DEFINE WORK worklib

The following example defines VERILOG_SUFFIX as the list .v, .vg, and .vb.

DEFINE VERILOG_SUFFIX (.v, .vg, .vb)

The following example defines the variable NCVLOGOPTS, which is used to specify command-line options for the ncvlog compiler.

DEFINE NCVLOGOPTS -messages -errormax 10 –update

1.2 UNDEFINE variable

Causes variable to become undefined. This statement is useful for removing definitions

That were defined in other files. If variable was not previously defined, you will not get an error message.

UNDEFINE NCUSE5X

1.3 INCLUDE filename

Reads filename as an hdl.var file.

Use INCLUDEE to include the variable definitions contained in the specified file. The pathname can be absolute or relative. If it is relative, it is relative to the hdl.var file in which it is defined.

Examples:

INCLUDE ~/my_hdl.var

INCLUDE /users/${USER}/hdl.var

1.4 Example hdl.var File

# Define the work library

DEFINE WORK worklib

# Define valid Verilog file extensions

DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg)

# Define valid VHDL file extensions

DEFINE VHDL_SUFFIX (.vhd, .vhdl)

# Specify command-line options for the ncvhdl compiler

DEFINE NCVHDLOPTS -messages -errormax 10

# Specify command-line options for the ncvlog compiler

DEFINE NCVLOGOPTS -messages -errormax 10 -ieee1364

# Specify command-line options for the elaborator

DEFINE NCELABOPTS -messages -errormax 10 -ieee1364 -plinooptwarn

# Specify the simulation startup command file

DEFINE NCSIMRC /usr/design/simrc.cmd