Promo of the Season 5 of Lost

The 5th season of the serial Lost will return in 2009. Recently, the ABC company has released the promo of the season 5.
Please click to this site:
http://www.lostreview.com/2008/10/lost-season-5-promo.cfm
May you enjoy it!

Parameter usage(Verilog-2001 VS Verilog-1995)

Let's set an example to indicate these differeces bewtween Verilog-1995 and Verilog-2001.

Example1 :

module myreg (q, d, clk, rst_n);
parameter Trst = 1,
Tckq = 1,
SIZE = 4,
VERSION = "1.1";
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= #Trst 0;
else q <= #Tckq d;
endmodule


module bad_wrapper (q, d, clk, rst_n);
output [7:0] q;
input [7:0] d;
input clk, rst_n;
// illegal parameter passing example
myreg #(.,.,8) r1 (.q(q), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

In order to use the parameter redefinition syntax when instantiating a module, all parameter values up to and including all values that are changed, must be listed in the myreg instantiation. For the module of Example 1, the first two parameter values must be listed, even though they do not change, followed by the new value for the
SIZE parameter, as shown in Example 2.

module good_wrapper (q, d, clk, rst_n);
output [7:0] q;
input [7:0] d;
input clk, rst_n;
// the first two parameters must be
// explicitly passed even though the
// values did not change
myreg #(1,1,8) r1 (.q(q), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

Aware of this limitation, engineers have frequently rearranged the order of the parameters to make sure that the most frequently used parameters are placed first in a module, similar to the technique described by Thomas and Moorby[4].

Despite the limitations of Verilog-1995 parameter redefinition, it is still the best supported and cleanest method for modifying the parameters of an instantiated
module. Verilog-2001 actually enhances the above parameter redefinition capability by adding the ability to pass the parameters by name, similar to passing port connections by name.

Example 2: to indicate how to instant myreg in Verilog-2001

module demuxreg (q, d, ce, clk, rst_n);
output [15:0] q;
input [ 7:0] d;
input ce, clk, rst_n;
wire [15:0] q;
wire [ 7:0] n1;
not u0 (ce_n, ce);
regblk #(.SIZE( 8)) u1
(.q(n1), .d (d), .ce(ce),
.clk(clk), .rst_n(rst_n));
regblk #(.SIZE(16)) u2
(.q (q), .d({d,n1}), .ce(ce_n)
.clk(clk), .rst_n(rst_n));
endmodule
module regblk (q, d, ce, clk, rst_n);
parameter SIZE = 4;
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input ce, clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else if (ce) q <= d;
endmodule

NetFPGA

Today, I sufured on the internaet, and came across a good FPGA study website. So I recmend to you. hope you enjoy it! It is indeed good!

Hope to join it to make a progress together with all the FPGA lover of all over the world.

It is http://www.netfpga.org/home.php

Its Introduction:

The NetFPGA enables researchers and students to build working prototypes of high-speed, hardware-accelerated networking systems. The NetFPGA has been used in the classroom to teach students how to build Gigabit Ethernet (GigE) switches and Internet Protocol (IP) routers that use hardware rather than software to forward packets.

opencore start

From now no, I am decided to study some projects in the opencore website in my sparetime.

Let us to come on together!

Today let's to review the OPENRISC CORE! I will put it into the table step by step, please focus on my blog with me! Thanks!

1)first stage Introduction

OpenRISC 1000: OpenRISC 1200

Introduction

The aim of this project is to design and maintain an OpenRISC 1200 IP Core. OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.


Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.

By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.

Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.

When implemented in a worst-case 0.18u 6LM process it should provide over 150 dhrystone 2.1 MIPS at 150MHz and 150 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class (typical corner 250MHz). The default OR1200 configuration is about 40k ASIC gates.

"Last Lecutre" of Prof. Randy Pausch

These words are abstrcted from the "Last Lecutre" of Prof. Randy Pausch. If you don't know who Randy is, i strogyly recommend to refer the website: http://download.srv.cs.cmu.edu/~pausch/news/index.html
May you enjoy it!


i. Helping others.

帮助他人。

ii. Never lose the childlike wonder. It's what drives us.

永远不要失去好奇心，它是人类前进的动力。

iii. Loyalty is a two way street.

诚以待人，这样别人也会忠实地对待你。

iv. Never give up.

永远不要放弃。

v. You can't get there alone. People have to help you. You get people to
help you by telling the truth.

你不能单打独斗，必须有人来帮你。只要你讲真话，就会有人来帮你。

vi. Apologize when you screw up and focus on other people, not on yourself.

当你把事情搞砸，首先要向别人道歉，首先关心他们的损失，而不是你自己的损失。

vii. When you do the right thing, good stuff has a way of happening.

如果你做了正确的事，好的结果自然会发生。

viii. Get a feedback loop and listen to it.

注意倾听反馈。

ix. Show gratitude.

感恩。

x. Don’t complain. Just work harder.

不要抱怨，而要加倍努力。

xi. Be good at something, it makes you valuable.

要有一技之长，它使你有价值。

xii. Work hard.

努力再努力。

xiii. Find the best in everybody.

注意发现他人的优点。

xiv. Be prepared. Luck is truly where preparation meets opportunity.

做好准备。所谓幸运，真的是机会和准备的结合。

Verilog “wait” Statement usage

The wait Statement

Definition

The wait statement is used as a level-sensitive control. The syntax is:

wait (expression) statement

The processor waits when the expression is FALSE. When the expression is TRUE, the statement is executed.

The expression is treated as a Boolean value, therefore wait responds to TRUE and FALSE only. Values '0', 'x' and 'z' are FALSE. Logic '1' is TRUE.

Comparison Between Event and Level Sensitive Processes

An example of an event-driven control is given below as a comparison to the level-sensitive control which will be described later.

always @(start) #10 go = ~go;

This process uses the @(expression) to trigger the process. The statement will be executed whenever there is an event on the start signal.

In comparison the following example illustrates a level-sensitive control:

forever wait(start) #10 go = ~go;

The process waits until start is `1'. When the start expression is TRUE, the go signal toggles after 10 time units. If start continues to stay `1' then go will continue to toggle after every 10 time units due to the forever definition. The toggling statement will only stop when start returns to `0'.

An event sensitive process is triggered by the edge on a control signal, while a level sensitive process is triggered by the value on the control signal.

Applications Of The wait Statement

The wait statement can be used to:

* Synchronise concurrent processes
* Hand shake between concurrent processes

The above example of a wait statement is also an example of synchronising. If more than one process is controlled by the start signal in a similar manner to that above, then when start goes high, several processes will start to run together. Thus they have been synchronised using the start signal.

The following is an example of hand shaking. The waveform below also refers to this example.

Process 1:

always begin
read = 1;
forever begin
wait (write)
// manipulate data
storeddata = datain;
#10;
read = 0;
wait (!write)
read = 1;
end // forever begin
end // always begin

Process 2:

always begin
write = 0;
forever begin
wait (read)
datain = $random;
$display($time, "datain = %b", datain);
// data read in
write = 1;
wait (!read)
write = 0;
end // forever begin
end // always begin

Both the processes run concurrently, so read and write are initialised to '1' and '0' respectively. Process 1 then waits for a '1' on the write signal. Process 2 is waiting for a '1' on the read signal. Because read is initialised to '1', process 2 continues (A). The data coming in is stored in a temporary register called datain. The write signal is then changed to a '1' to signify that the input data has been read (B). Process 2 is now waiting for the read signal to become '0'.

Process 1 is triggered by write being '1'. The data in the temporary register can now be safely manipulated and then written to another register called storeddata. When this process has completed, read is set to '0' to signify that the data has been successfully transferred (C). This triggers process 2 which has been waiting for read to go to '0'. Process 2 changes write to '0' to say it is ready to receive data whenever process 1 is ready (D). This triggers the last wait statement in process 1 to change read to '1'. The two processes are now back in their initial states and waiting to repeat the above procedure.

This hand shaking method avoids process 1 trying to manipulate the incoming data before it has been fully received. It also stops process 2 reading in more data before process 1 has finished with the previously read data.

The Difference Between wait And while

The wait statement should not be confused with the while statement. Two examples are given below:

always begin always begin
wait(start) while(start)
go = 1; go = 1;
stop = 0; stop = 0;
end end

The wait statement will halt the process when start = '0'. The whole process will not procede until the start expression is TRUE. When start = '1', go will be set to '1' and then stop will be set to '0'.

The while statement will not set go to '1' unless start is '1'. If start is '0', the while statement will not set go to '1' but stop will be set to '0'. The while statement does not stop the whole process. It only stops the statement within the while loop from being executed.

Summary

The wait statement can be used for synchronising or hand shaking between concurrent processes as shown in the examples above. The process waits until the expression is true. It then executes the statement.

(fwd)Shenzhen Integrated Circuit Design Industrial Center Licenses Low-Power Cores from MIPS Technologies

Shenzhen Integrated Circuit Design Industrial Center Licenses Low-Power Cores from MIPS Technologies

Processor Cores Expand IP Portfolio for China IC Design Industry Base

MOUNTAIN VIEW, Calif., Sept. 30 /PRNewswire-FirstCall/ -- MIPS Technologies, Inc. (NASDAQ:MIPS) , a leading provider of industry-standard architectures, processors and analog IP for digital consumer, home networking, wireless, communications and business applications, today announced that Shenzhen Integrated Circuit Design Industrial Center has licensed its low-power MIPS32(R) M4K(R) and MIPS32(R) 4Kc(TM) processor cores for next generation IC designs. The agreement provides Chinese IC design firms with access to some of the industry's most cost-effective, low-power cores, along with the broad ecosystem of tools, software and services that support the industry standard MIPS(R) architecture.

"We are focused on expanding our silicon intellectual property (IP) portfolio with the most popular IP to assist IC designers in China in designing successful SoCs for their customers," said Shengming Zhou, director of Shenzhen Integrated Circuit Design Industrial Center. "We believe that IP reuse is critical to furthering the IC design industry in China, and are pleased to engage with MIPS Technologies for its trusted and proven technology. With a great balance of power, performance and price, the MIPS cores are applicable for a wide variety of next-generation embedded designs and microcontroller-based applications."

"We are pleased that Shenzhen Integrated Circuit Design Industrial Center has licensed MIPS cores as part of its silicon IP portfolio for China's SoC designers," said Brad Holtzinger, vice president of worldwide sales at MIPS Technologies. "The Center and others like it are clearly an important resource for growing China's IC design industry. We look forward to providing MIPS Technologies' cores to enable the Center's partners and customers to bring differentiated products to market on-time at the lowest possible cost."

MIPS32(R) 4K(R) cores -- successfully implemented in hundreds of SoC designs -- are designed for SoC applications that require an easy-to-use and cost-efficient embedded processor. The M4K core sets a new standard for 32-bit cores targeted for embedded designs and microcontroller applications. It features high frequency, small die area and very low power consumption.

About Shenzhen Integrated Circuit Design Industrial Center

One of seven IC design industry bases supported by the Chinese Ministry of Science and Technology, Shenzhen Integrated Circuit Design Industrial Center offers tools, resources and services to encourage and support local chip design enterprises in design and product innovation. The Center helps small and medium-sized enterprises with product development, company incubation, and personnel support to lower barriers to market entry. By providing key electronic design technologies, intellectual property, tools, design consulting and chip design services, as well as establishing strategic alliances and technical partnerships, the Center is contributing to the development of the local IC design industry and growth of China's economy. For more information, visit http://www.szicc.net/.

About MIPS Technologies, Inc.

MIPS Technologies, Inc. (NasdaqGS: MIPS) is the world's second largest semiconductor design IP company and the number one analog IP company worldwide. With more than 250 customers around the globe, MIPS Technologies is the only company that provides a combined portfolio of processors, analog IP and software tools for the embedded market. The company powers some of the world's most popular products for the digital entertainment, home networking, wireless, and portable media markets -- including broadband devices from Linksys, DTVs and digital consumer devices from Sony, DVD recordable devices from Pioneer, digital set-top boxes from Motorola, network routers from Cisco, 32-bit microcontrollers from Microchip Technology and laser printers from Hewlett-Packard. Founded in 1998, MIPS Technologies is headquartered in Mountain View, California, with offices worldwide. For more information, contact (650) 567-5000 or visit http://www.mips.com/.

MIPS, MIPS32, 4Kc and M4K are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners.

Source: MIPS Technologies, Inc.