$test$plusagrs systme function in verilog-2001
Verilog allows users to create new simulation invocation options.
The $test$plusargs system function checks to see if a “plus” option was used when simulation was invoked.
Example : NCverilog test.vchip.v +test2
Pattern file code can be writen as the followings:
initial
begin
if($test$plusargs(“test1”))
$readmemh(“test1.dat”,vectors);
elseif($test$plusargs(“test2”))
$readmemh(“test2.dat”,vectors);
elseif($test$plusargs(“test3”))
$readmemh(“test3.dat”,vectors);
else $display(“Error:notestoptionspecified”);
end
Labels: verilog-2001
posted by lubee @ 8:46 AM
1 Comments:
have you observed that this syntax doesn't allow one option to be subset of the other.
Example:
initial
begin
if($test$plusargs(“testONE”))
$readmemh(“test1.dat”,vectors);
elseif($test$plusargs(“testONETWO”))
$readmemh(“test2.dat”,vectors);
elseif($test$plusargs(“testONETWOTHREE”))
$readmemh(“test3.dat”,vectors);
else $display(“Error:notestoptionspecified”);
end
------
Here, string testONE is a subset of following other two options.
So when you run the sim with:
ncverilog myrtl.v +testONE
You'll see that all 3 branches of the if-else got executed.
do you know any way to avoid that from happening?
(apart from the obvious one, which is name them ONEtest, ONETWOtest, ONETWOTHREEtest. That can be tedious thing to do over the whole database with many such combinations pre-existing).
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