systemverilog_example:Parity

//-----------------------------------------------------
// Design Name : parity_using_assign
// File Name   : parity_using_assign.sv
// Function    : Parity using assign
// Coder      : Deepak Kumar Tala
//-----------------------------------------------------
module parity_using_assign (
input   wire [7:0] data_in    , //  8 bit data in
output  wire       parity_out   //  1 bit parity out
);
//--------------Code Starts Here-----------------------
assign parity_out =  (data_in[0] ^ data_in[1]) ^ 
                    (data_in[2] ^ data_in[3]) ^
                    (data_in[4] ^ data_in[5]) ^ 
                    (data_in[6] ^ data_in[7]);

endmodule

Using function- I
		1 //----------------------------------------------------- 2 // Design Name : parity_using_function 3 // File Name : parity_using_function.sv 4 // Function : Parity using function 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module parity_using_function ( 8 input wire [7:0] data_in , // 8 bit data in 9 output wire parity_out // 1 bit parity out 10 ); 11 //--------------Code Starts Here----------------------- 12 function parity; 13 input [31:0] data; 14 begin 15 parity = (data_in[0] ^ data_in[1]) ^ 16 (data_in[2] ^ data_in[3]) ^ 17 (data_in[4] ^ data_in[5]) ^ 18 (data_in[6] ^ data_in[7]); 19 end 20 endfunction 21 22 assign parity_out = parity(data_in); 23 24 endmodule You could download file sv_examples here
		Using function- II
		1 //----------------------------------------------------- 2 // Design Name : parity_using_function2 3 // File Name : parity_using_function2.v 4 // Function : Parity using function 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module parity_using_function2 ( 8 input wire [31:0] data_in , // 8 bit data in 9 output reg parity_out // 1 bit parity out 10 ); 11 //--------------Code Starts Here----------------------- 12 function parity; 13 input [31:0] data; 14 integer i; 15 begin 16 parity = 0; 17 for (i = 0; i < id="sc"> = i + 1) begin 18 parity = parity ^ data[i]; 19 end 20 end 21 endfunction 22 23 always_comb 24 begin 25 parity_out = parity(data_in); 26 end 27 28 endmodule You could download file sv_examples here
		And the Practical One
		1 //----------------------------------------------------- 2 // Design Name : parity_using_bitwise 3 // File Name : parity_using_bitwise.sv 4 // Function : Parity using bitwise xor 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module parity_using_bitwise ( 8 input wire [7:0] data_in , // 8 bit data in 9 output wire parity_out // 1 bit parity out 10 ); 11 //--------------Code Starts Here----------------------- 12 assign parity_out = ^data_in; 13 14 endmodule