systemverilog code example_1:MUX

Mux : Using assign Statement

//-----------------------------------------------------
// Design Name : mux_using_assign
// File Name   : mux_using_assign.sv
// Function    : 2:1 Mux using Assign
// Coder      : Deepak Kumar Tala
//-----------------------------------------------------
module  mux_using_assign (
input  wire  din_0      , // Mux first input
input  wire  din_1      , // Mux Second input
input  wire  sel        , // Select input
output wire  mux_out      // Mux output
);
//-------------Code Start-----------------
assign mux_out = (sel) ? din_1 : din_0;

endmodule //End Of Module mux


//-----------------------------------------------------
// Design Name : mux_using_if
// File Name   : mux_using_if.sv
// Function    : 2:1 Mux using If
// Coder      : Deepak Kumar Tala
//-----------------------------------------------------
module  mux_using_if(
input  wire  din_0      , // Mux first input
input  wire  din_1      , // Mux Second input
input  wire  sel        , // Select input
output reg   mux_out      // Mux output
);
//-------------Code Starts Here---------
always_comb
begin : MUX
 if (sel == 1'b0) begin
     mux_out = din_0;
 end else begin
     mux_out = din_1 ;
 end
end

endmodule //End Of Module mux


//-----------------------------------------------------
// Design Name : mux_using_case
// File Name   : mux_using_case.sv
// Function    : 2:1 Mux using Case
// Coder      : Deepak Kumar Tala
//-----------------------------------------------------
module  mux_using_case(
input  wire  din_0      , // Mux first input
input  wire  din_1      , // Mux Second input
input  wire  sel        , // Select input
output reg   mux_out      // Mux output
);
//-------------Code Starts Here---------
always @ (*)
MUX : begin
case (sel)
   1'b0 : mux_out = din_0;
   1'b1 : mux_out = din_1;
endcase
end

endmodule //End Of Module mux