(fwd)A guideline to achieve faster timing closure

I had wrote my Register Transfer Language(RTL) for a specific functionality.so i say my Module(I.P.) is ready in terms of functionality.

Now the question comes is what is timing closure and why it could be an issue.

Now lets list down.

1. Library Characterizing: "Chip designing is all about Modeling the silicon", and how well we characterize the silicon, is all the game. So initially let us assume our process technology is say "32nm", for example: Now we need to develop a test-chip, having modules (digital & analog), and study our silicon timings. Now the toughest job is to generate library views(formats specific to each tool understandable formats).There is a bit of timing in accuracy possible in the views across the formats.

2. Modeling of Wires: How well do we co-relate the timing achieved in synthesis and the timing after place and route.

Usually the synthesis and place and route (P & R) tools are different.

let us take for example:

For synthesis: Synopsys Design Compiler

For placement and Route tool : Magma Blast fusion.

Synthesis Tool Timing:

In the synthesis tool, in order to model the wires we use a concept called as "Wireload models", Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available.

Place & Route Tool Timing:

In the placement and Route Tool, there is no concept based on statistics for the wire-delay values, everything is real, what i mean here , this will what be seen close in the silicon.

So in this scenario, The timing convergence is really required to attain closure in "Synthesis Vs placement & Route Tool" otherwise called as "Timing convergence or Timing correlation Frontend Vs Backend".

3. Multi-mode Scenario Timing Convergence:

Todays world , we need more but we are greedy as well.

We need more functionality, more interfaces, typically means more pin-count, but more pin count needs bigger package cost. We are neither ready for a bigger package cost, so now what is the alternative , nor comprise on reducing our interfaces. so here comes the solution "Pin-muxing". it means, the same pin will act for one or more interfaces depending upon the chip configuration and their timing requirement varies depending on their electrical Specification requirement.

As on date, most of the placement and routing tool cannot operate on the Multimode timing requirement scenario and can read and perform with multiple constraints file, it is very difficult in the tools perspective also to understand multiple constraints and preserve multiple arrival time requirements at each node with different values, it is a really tough game, in optimizing memory requirements, run time requirements and all that stuff in terms of EDA tools.

So if the path is not optimized for multi-mode and just optimized for a single worst case mode(which is very tough to predict what could be a worst case scenario) and give it to placement and routing tool, then while running Static Timing Analysis(STA) we could visualize lot of surprises, which will be very much new in terms of performance.

4. On chip Variations:

Todays world everything changes, what to model and what not , i am going crazy.

As per the famous quote by John.F. Kennedy "Change is the law of Life", which is very much true for semiconductor industry. And Variation is all about "Rate of Change".

Wafer Variations: Every wafer can vary in terms of timing performance, it is hard to predict, there could fast lot , slow lot, typical lot in terms of timing performance.

Intra die Variations: In a single wafer, distribution dies across the wafer will vary in terms of timing performance.

Inter die Variations: Within a die/chip, there could be timing performance issue..

Now the Art is all about modeling these variations and prooving our Designs will be working for these variations in real time scenario and qualify the Design for Robustness.