Debussy Interface in Verilog

Overview Debussy is a debugging system developed by Novas Software. Riviera-PRO can work with Debussy in two modes: Post-processing Mode In the post-processing mode simulation and debugging are two separate stages. First, Riviera-PRO is used to simulate the design. During simulation Riviera-PRO dumps required data (i.e. signal waveforms) to a Fast Signal Database (FSDB). Once the simulation process is over, the design can be loaded into Debussy. Debussy will read the signal history from the FSDB database created by Riviera-PRO. Dumping data to the FSDB database can be controlled either directly from Verilog source code (with FSDB tasks) or with macro commands. Macro commands (and FSDB tasks) can be invoked interactively from the Console or placed in macro files. Interactive Mode In the interactive mode Riviera-PRO acts as a slave application for Debussy and can be controlled directly from the Debussy GUI. Debussy sends commands to Riviera-PRO and reads simulation data from it. Using the interactive mode requires some initial setup such as compiling the project in Riviera-PRO, verifying the list of available PLI application and preparing the debussy.rc file (templates are available). NOTE: Riviera-PRO for Solaris and Riviera-PRO for Linux uses version 6.1 of the FSDB writer module (developed by Novas Software). Riviera-PRO for Windows uses FSDB writer module version 5.4. This is the latest version provided by Novas on this platform. Contents: Post-processing Mode Interactive Mode Debussy Resource File Supported FSDB Tasks Post-processing Mode Dumping FSDB databases from Verilog designs is controlled with FSDB tasks. Tasks can either be placed directly in Verilog source code, used in a macro file (alongside regular macro commands) or issued interactively from the Console. To control writing data to the FSDB database, place the appropriate tasks directly in the source code, for example: initial $fsdbDumpvars(0, V_BJACK_tb); Refer to Debussy documentation for details on using FSDB tasks. If you do not want to modify your Verilog source code, you can call FSDB tasks directly from the Console, for example: asim V_BJACK_tb $fsdbDumpfile("simdata.fsdb") $fsdbDumpvars(0, V_BJACK_tb) run -all Simulation data is automatically flushed to the FSDB database when simulation is finished with the endsim command. The simulation process can be automated with a macro file. The macro can include all supported FSDB tasks. NOTE: FSDB tasks are located in the libfsdbwriter.so (Unix, Linux) or fsdbwriter.dll (Windows) library. This library must be included in the list of PLI applications for the FSDB tasks to work. To check PLI applications available to Riviera-PRO, select Tools | Simulation Options from the menu, go to the Verilog tab and click the PLI Applications button. By default, the libfsdbwriter.so (Unix, Linux) or fsdbwriter.dll (Windows) library is included in the list of PLI applications. Interactive Mode Before using Debussy with Riviera-PRO in the interactive mode, the environment should be set up in Riviera-PRO. In Verilog designs this requires creating a library, compiling Verilog source files, checking the list of PLI applications visible from the current directory and changing the hierarchy separator to Verilog-like. Debussy can then be started with the start_debussy script (delivered with Riviera-PRO). Both Riviera-PRO and Debussy should work in the same directory (referred to as the project directory). Compiling Source Files in Riviera-PRO Compilation should be run in the project directory. The directory can be selected in the system shell before Riviera-PRO is started with the rungui script or directly in the Riviera-PRO environment (with the Change Directory command from the File menu). After selecting the directory, create a new library and set is as the default working library. The name of the default working library is displayed in the Library combo box in the Console. After creating the library, you can compile project source files. Use the Compile command from the Compilation menu or the alog macro command. If you want to use line debug, make sure the -dbg switch is passed to alog. Changing the Hierarchy Separator To ensure proper communication between Riviera-PRO and Debussy, the hierarchy separator must be changed from VHDL like to Verilog like. To change the separator, choose Simulation Options from the Simulation menu and choose Verilog like on the General tab. Verifying the List of PLI Applications Tasks for writing FSDB database reside in the libfsdbwriter.so (Unix, Linux) or fsdbwriter.dll (Windows) library. This library should be included in the list of PLI applications visible from the current directory. To check PLI applications available to Riviera-PRO, select Tools | Simulation Options from the menu, go to the Verilog tab and click the PLI Applications button. The libfsdbwriter.so (Unix, Linux) or fsdbwriter.dll (Windows) library is by default included in the list of PLI applications. If it was removed from the list, use the Add button to restore the default. The project data is now ready. You can quit Riviera-PRO and start Debussy. Debussy should be started from the project directory, otherwise configuration settings stored in the project directory will not be available. Starting Debussy Debussy can be started with the start_debussy script included with Riviera-PRO. The script is located in the etc/ subdirectory of the Riviera-PRO installation directory. Command line switches for Debussy can be passed directly to start_debussy, for example: /etc/start_debussy -f run.f NOTE: The run.f file contains a list of project source files. Before starting Debussy, the start_debussy script checks if the project directory contains the debussy.rc file. If the file cannot be found, the script copies the template verilog.rc file to the project directory and renames it debussy.rc. The verilog.rc file included with Riviera-PRO includes additional sections that make Riviera-PRO visible to Debussy. NOTE: If the project directory already contains the debussy.rc file, the script will not overwrite it. If the debussy.rc file does not include sections required by Riviera-PRO you can either: Close Debussy, rename the debussy.rc file and start Debussy again with the start_debussy script. The script will copy the template debussy.rc file to the current directory, as described above. Add add the appropriate sections manually. See Debussy Resource File for details. Starting the Interactive Mode To switch Debussy to the interactive mode, use the Interactive Mode command from the Tools menu. Debussy will display an additional taskbar. Clicking the Run/Continue button will initialize Riviera-PRO. Note that the Riviera-PRO console replaces the Debussy console. The console is fully interactive. It displays messages from Riviera-PRO and it can also be used to enter Riviera-PRO macro commands or invoke FSDB tasks. After switching to the interactive mode, call the $fsdbDumpvars task: $fsdbDumpvars This tells Riviera-PRO to dump signal change information to the FSDB file. Simulation data from the FSDB file is then read by Debussy. You can now select Active Annotation from the Source menu to see how Debussy annotates the source code with simulation data generated by Riviera-PRO. For further details on using Debussy refer to Debussy documentation. NOTE: To check if Riviera-PRO is the default simulator for the interactive mode choose Tools | Options | Preferences from the Debussy menu and then select the Simulation tab in the Preferences window. Riviera-PRO is listed under the name Aldec. Debussy Resource File The debussy.rc resource file contains Debussy configuration settings. The file is automatically created in the directory you run Debussy from. The template debussy.rc files are located in the etc/ subdirectory of the Debussy installation directory. The files are renamed vhdl.rc and verilog.rc. The verilog.rc file contains settings required in Verilog designs. The verilog.rc file is automatically copied to the current directory and renamed debussy.rc if you start Debussy with the start_debussy script: start_debussy The start_debussy script is located in the etc/ subdirectory of Riviera-PRO installation directory. If the debussy.rc file already exists in the current directory, the start_debussy script will not overwrite it. If the original debussy.rc does not contain entries required by Riviera-PRO, you can either add the required entries manually or rename the original debussy.rc file and run start_debussy again. A list of changes that have to be applied to the debussy.rc file to enable integration of Debussy and Riviera-PRO is shown below. Note that different settings are required for VHDL and Verilog. This application note lists only changes required for Verilog designs. See a separate application note for VHDL. In the [ThirdParty] section, add Aldec to the vendor list: [ThirdParty] ThirdPartySimTool = vendor1 vendor2 aldec Additionally, you can set Riviera-PRO to be the default simulator by setting the thirdpartyIdx key in the [Simulation] section to the index of Aldec in ThirdPartySimTool list. In the above example it is 2 (list items are counted from 0): [Simulation] simType = aldec thirdpartyIdx = 2 The following sections have to be added to the debussy.rc file that is going to be used with Verilog designs. [aldec] TPLanguage = Verilog TPName = Aldec TPPath = //etc/vsad TPOption = -init AddImportArgument = FALSE LineBreakWithScope = FALSE StopAfterCompileOption = "" TPPath contains the full path to the vsad script located in the etc/ subdirectory of the Riviera-PRO installation directory. Optionally, user defined commands can be set: [UserButton.aldec] Button1 = "Dump All Signals" "$fsdbDumpvars\n" Button2 = "Next 1000 Time" "run 1000\n" Button3 = "Next ? Time" "run ${Arg:Next Time}\n" Button4 = "Show Variable" "examine ${SelVar}\n" Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" Button6 = "Release Variable" "noforce ${SelVar}\n" Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" Button8 = "Dump Now" "$fsdbDumpflush" Button9 = "Dump Off" "$fsdbDumpoff\n" Button10 = "Dump On" "$fsdbDumpon\n" Supported FSDB Tasks The following FSDB tasks are supported in Verilog (for detailed usage information, refer to Debussy documentation): $fsdbDumpfile $fsdbDumpvars $fsdbDumpvarsToFile // only one argument is supported (i.e. the filename with the dumpscope) $fsdbDumpMem, $fsdbDumpMemNow $fsdbDumpon $fsdbDumpoff $fsdbDumpflush $fsdbVersion The following tasks are currently not supported: $fsdbAutoSwitchDumpfile, $fsdbSwitchDumpfile, $fsdbDumpStrength. Except for placing the tasks in the HDL source code, you can also invoke equivalent macro commands or tasks from the Console or from a macro file. (The names of the commands are the same as the names of the tasks, without the initial $ sign.)